FPGA design flow with automated test generation
vastutusandmed
G.Elst, K.-H.Diener, E.Ivask, J.Raik, R.Ubar
allikas
Proc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems : Potsdam, 1999
ilmumiskoht
[S.l.]
ilmumisaasta
leheküljed
p. 120-123
keel
inglise
Elst, G., Diener, K.-H., Ivask, E., Raik, J., Ubar, R. FPGA design flow with automated test generation // Proc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems : Potsdam, 1999. [S.l.], 1999. p. 120-123.