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Defect-oriented fault simulation and test generation in digital circuits

autor
Kuzmicz, W.
Pleskacz, Witold A.
Raik, Jaan
Ubar, Raimund-Johannes
vastutusandmed
W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar
allikas
IEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California
ilmumiskoht
Los Alamitos, CA
kirjastus/väljaandja
IEEE Computer Society
ilmumisaasta
2001
leheküljed
p. 365-371
leitav
https://ieeexplore.ieee.org/document/915257
märksõna
digitaaltehnika
sidevõrgud
rikked
defektid
testimine
simulatsioon
ISBN
0-7695-1025-6
märkused
Bibliogr.: 10 ref
Kuzmicz, W., Pleskacz, W., Raik, J., Ubar, R. Defect-oriented fault simulation and test generation in digital circuits // IEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California. Los Alamitos, CA : IEEE Computer Society, 2001. p. 365-371. https://ieeexplore.ieee.org/document/915257