Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
vastutusandmed
R. Leveugle, R. Ubar
ilmumiskoht
[S.l.]
ilmumisaasta
leheküljed
p. 353-358
keel
inglise
Leveugle, R., Ubar, R. Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation // Proceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 1998. [S.l.], 1998. p. 353-358.