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Jenihhin, Maksim (author)
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101
book article
Hybrid BIST time minimization for core-based systems with STUMPS architecture
Jervan, Gert
;
Eles, Petru
;
Peng, Zebo
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings
2003
/
p. 225-232 : ill
https://ieeexplore.ieee.org/document/1250116
book article
102
journal article EST
/
journal article ENG
Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuits
Jenihhin, Maksim
;
Squillero, Giovanni
;
Tihhomirov, Valentin
;
Kostin, Sergei
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Journal of electronic testing : theory and applications (JETTA)
2016
/
p. 273-289 : ill
https://doi.org/10.1007/s10836-016-5589-x
Journal metrics at Scopus
Article at Scopus
Journal metrics at WOS
Article at WOS
journal article EST
/
journal article ENG
103
book article
Identification and rejuvenation of NBTI-critical paths in nanoscale logic circuits
Jenihhin, Maksim
1st International Workshop on Reliability and Aging in Forthcoming Electronic Systems : May 28-29, 2015, Cluj-Napoca, Romania
2015
/
[1] p
book article
104
book article
Identifying NBTI-critical paths in nanoscale logic
Ubar, Raimund-Johannes
;
Vargas, Fabian
;
Jenihhin, Maksim
;
Raik, Jaan
;
Kostin, Sergei
;
Bolzani Poehls, Leticia
16th Euromicro Conference series on Digital System Design : DSD 2013 : proceedings : 4-6 September 2013, Santander, Spain
2013
/
p. 136-141 : ill
book article
105
journal article
Identifying untestable faults in sequential circuits using test path constraints
Viilukas, Taavi
;
Karputkin, Anton
;
Raik, Jaan
;
Jenihhin, Maksim
;
Ubar, Raimund-Johannes
;
Fujiwara, Hideo
Journal of electronic testing : theory and applications (JETTA)
2012
/
p. 511-521 : ill
https://link.springer.com/article/10.1007/s10836-012-5312-5
journal article
106
book article
IJTAG-compatible symptom-based SEU monitors for FPGA DNN accelerators
Cherezova, Natalia
;
Jenihhin, Maksim
;
Jutman, Artur
2024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)
2024
/
6 p. : ill
https://doi.org/10.1109/DTTIS62212.2024.10780417
Article at Scopus
Article at WOS
book article
107
book article
Implementation-independent functional test for transition delay faults in microprocessors
Oyeniran, Adeboye Stephen
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia
2020
/
p. 646-650
https://doi.org/10.1109/DSD51259.2020.00105
book article
108
book article
Implementation-independent functional test generation for RISC microprocessors
Oyeniran, Adeboye Stephen
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
VLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]
2019
/
p. 82-87 : ill
https://doi.org/10.1109/VLSI-SoC.2019.8920323
book article
109
book article
Implementation-independent test generation for a large class of faults in RISC processor modules
Jenihhin, Maksim
;
Oyeniran, Adeboye Stephen
;
Raik, Jaan
;
Ubar, Raimund-Johannes
24th Euromicro Conference on Digital System Design (DSD)
2021
https://doi.org/10.1109/DSD53832.2021.00090
book article
110
book article
An iterative approach to test time minimization for parallel hybrid BIST architecture
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Jervan, Gert
;
Peng, Z.
5th IEEE Latin-American Test Workshop - LATW 2004 : Cartagena, Colombia, 2004 : digest of papers
2004
/
p. 98-103 : ill
https://www.ida.liu.se/labs/eslab/publications/pap/db/latw04.pdf
book article
111
book article
An iterative approach to test time minimization for parallel hybrid BIST architectures
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Jervan, Gert
;
Peng, Z.
System-on-Chip Conference 2004 : Bastad, Sweden
2004
/
p. ?
https://www.ida.liu.se/labs/eslab/publications/pap/db/latw04.pdf
book article
112
book article
JÄNES : a NAS framework for ML-based EDA applications
Selg, Hardi
;
Jenihhin, Maksim
;
Ellervee, Peeter
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
2021
https://doi.org/10.1109/DFT52944.2021.9568321
book article
113
newspaper article
Kas tehisintellekt on väikeriigi demokraatia ja julgeoleku tugi või oht?
Vaaks, Eveliis
Trialoog
2025
https://trialoog.taltech.ee/kas-tehisintellekt-on-vaikeriigi-demokraatia-ja-julgeoleku-tugi-voi-oht/
newspaper article
114
book article
Keynote: cost-efficient reliability for Edge-AI chips
Jenihhin, Maksim
;
Taheri, Mahdi
;
Cherezova, Natalia
;
Ahmadilivani, Mohammad Hasan
;
Selg, Hardi
;
Jutman, Artur
;
Shibin, Konstantin
;
Tsertov, Anton
;
Devadze, Sergei
;
Kodamanchili, Rama Mounika
;
Rafiq, Ahsan
;
Raik, Jaan
;
Daneshtalab, Masoud
2024 IEEE 25th Latin American Test Symposium (LATS)
2024
/
2 p
https://doi.org/10.1109/LATS62223.2024.10534610
Article at Scopus
book article
Related publications
1
Methods for reliability assessment and enhancement of deep neural networks hardware accelerators = Süvanärvivõrkude riistvara kiirendite töökindluse hindamine ja täiustamine
115
book article
Layout to logic defect analysis for hierarchical test generation
Jenihhin, Maksim
;
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Pleskacz, Witold A.
;
Rakowski, Michal
Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland
2007
/
p. 35-40 : ill
http://dx.doi.org/10.1109/DDECS.2007.4295251
book article
116
book article
Localization of bugs in processor designs using zamiaCAD framework
Tšepurov, Anton
;
Tihhomirov, Valentin
;
Jenihhin, Maksim
;
Raik, Jaan
13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions : Austin, USA, December 10–12, 2012
2012
/
p. 1-6
https://ieeexplore.ieee.org/document/6519733
book article
117
book article
Measuring and identifying aging-critical paths in FPGAs
Pfeifer, Petr
;
Raik, Jaan
;
Jenihhin, Maksim
;
Ubar, Raimund-Johannes
;
Pliva, Zdenek
MEDIAN 2015 : the 4th Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : March 13, 2015, Grenoble, France
2015
/
p. 56-61 : ill
book article
118
book article
A methodology for automated mining of compact and accurate assertion sets
Heidari Iman, Mohammad Reza
;
Raik, Jaan
;
Jenihhin, Maksim
;
Jervan, Gert
;
Ghasempouri, Tara
2021 IEEE Nordic Circuits and Systems Conference (NorCAS) : Oslo, Norway, October 26-27
2021
/
7 p. : ill
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9599865
https://doi.org/10.1109/NorCAS53631.2021.9599865
book article
119
dissertation
Methods for reliability assessment and enhancement of deep neural networks hardware accelerators = Süvanärvivõrkude riistvara kiirendite töökindluse hindamine ja täiustamine
Taheri, Mahdi
2025
https://www.ester.ee/record=b5728368*est
https://digikogu.taltech.ee/et/Item/9cf79768-17bc-44ec-a828-e4ccf6cf93f1
https://doi.org/10.23658/taltech.4/2025
dissertation
Related publications
14
APPRAISER : DNN fault resilience analysis employing approximation errors
DeepAxe : a framework for exploration of approximation and reliability trade-offs in DNN accelerators
Special session : approximation and fault resiliency of DNN accelerators
A systematic literature review on hardware reliability assessment methods for deep neural networks
AdAM: adaptive fault-tolerant approximate multiplier for edge DNN accelerators
Special session: reliability assessment recipes for DNN accelerators
Keynote: cost-efficient reliability for Edge-AI chips
Enhancing fault resilience of QNNs by selective neuron splitting
DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs’ Reliability Assessment
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs
Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability
120
dissertation
Methods to optimize functional safety assessment for automotive integrated circuits = Meetodid autotööstuse kiipide funktsionaalse ohutuse hindamise optimeerimiseks
Bagbaba, Ahmet Cagri
2022
https://doi.org/10.23658/taltech.9/2022
https://digikogu.taltech.ee/et/Item/58b0b89d-b1ba-4a73-ba53-850910d697b5
https://www.ester.ee/record=b5491885*est
dissertation
Related publications
10
Accelerating transient fault injection campaigns by using Dynamic HDL Slicing
Efficient fault injection based on dynamic HDL slicing technique
Special session : AutoSoC - a suite of open-source automotive SoC benchmarks
Representing gate-level SET faults by multiple SEU faults on RT-level
Improving the confidence level in functional safety simulation tools for ISO 26262
Use of formal methods for verification and optimization of fault lists in the scope of ISO26262
Efficient methodology for ISO26262 functional safety verification
Combining fault analysis technologies for ISO26262 functional safety verification
Determined-safe faults identification : a step towards ISO26262 hardware compliant designs
Automated identification of application-dependent safe faults in automotive systems-on-a-chips
121
journal article
Mixed hierarchical-functional fault models for targeting sequential cores
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Viilukas, Taavi
;
Jenihhin, Maksim
Journal of systems architecture
2008
/
3/4, p. 465-477 : ill
https://www.sciencedirect.com/science/article/abs/pii/S1383762107001166
journal article
122
book article
Mixed-level identification of fault redundancy in microprocessors
Oyeniran, Adeboye Stephen
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Gürsoy, Cemil Cem
;
Raik, Jaan
LATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 2019
2019
/
6 p. : ill
https://doi.org/10.1109/LATW.2019.8704591
book article
123
book article
ML-based online design error localization for RISC-V implementations
Selg, Hardi
;
Jenihhin, Maksim
;
Ellervee, Peeter
;
Raik, Jaan
2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS) : IOLTS 2023 : July 3rd-5th, 2023, Platanias, Chania (Crete), Greece : proceedings
2023
/
7 p.
https://doi.org/10.1109/IOLTS59296.2023.10224864
book article
124
book article
MLC: a machine learning based checker for soft error detection in embedded processors
Nosrati, Nooshin
;
Jenihhin, Maksim
;
Navabi, Zainalabedin
Proceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 2022
2022
/
Code 183305
https://doi.org/10.1109/IOLTS56730.2022.9897309
Article at Scopus
Article at WOS
book article
125
book article
Modeling for multi-view interference analysis of design aspects in MPSoC designs
Vain, Jüri
;
Apneet Kaur
;
Tsiopoulos, Leonidas
;
Raik, Jaan
;
Jenihhin, Maksim
RESCUE 2017 : Workshop on Reliability, Security and Quality : ETS17 Fringe Workshop, May 25-26, 2017, Limassol, Cyprus
2017
/
p. 1-6
http://www.ets17.org.cy/workshop/rescue-workshop.html
book article
Number of records 214, displaying
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17
1.
Jenihhin, Maksim
2.
Andrijaškin, Maksim
3.
Antonov, Maksim
4.
Butsenko, Maksim
5.
Dolinin, Maksim
6.
Gorev, Maksim
7.
Kuleša, Maksim
8.
Maksim, I.
9.
Maksim, Tiit
10.
Mõttus, Maksim
11.
Ošeka, Maksim
12.
Radzvilovits, Maksim
13.
Ruchkin, Maksim
14.
Saat, Maksim
15.
Sitnikov, Maksim
16.
Säkki, Maksim
17.
Zelenski, Maksim
name of the person
9
1.
Jenihhin, Maksim
2.
Jenihhin, Maksim, 1981-
3.
Antonov, Maksim
4.
Butsenko, Maksim
5.
Gorev, Maksim
6.
Gorki, Maksim, pseud., 1868-1936
7.
Ošeka, Maksim
8.
Ošeka, Maksim, 1988-
9.
Saat, Maksim
CV
9
1.
Jenihhin, Maksim
2.
Antonov, Maksim
3.
Butsenko, Maksim
4.
Gazizov, Maksim 1918-?
5.
Oseka, Maksim
6.
Osheka, Maksim
7.
Ošeka, Maksim
8.
Saat, Maksim
9.
Säkki, Maksim
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