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On coverage of timing related faults at board levelJutman, Artur; Aleksejev, Igor; Devadze, Sergei2016 21st IEEE European Test Symposium (ETS) : May 23rd-26th 2016, Amsterdam, The Netherlands : proceedings2016 / [2] p. : ill https://doi.org/10.1109/ETS.2016.7519295

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302

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On efficient logic-level simulation of digital circuits represented by the SSBDD modelJutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes23rd International Conference on Microelectronics : MIEL 2002, Niš, Yugoslavia, 12-15 May 2002 : proceedings. Volume 22002 / p. 621-624 : ill https://ieeexplore.ieee.org/document/1003334

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303

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On multiple fault detection in combinational logic circuitsBirger, AlexanderBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 225-228

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304

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On NBTI-induced aging analysis in IEEE 1687 reconfigurable scan networksDamljanovic, Aleksa; Squillero, Giovanni; Gürsoy, Cemil Cem; Jenihhin, MaksimVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 335-340 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920313

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305

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On the estimation of complex circuits functional failure rate by machine learning techniquesLange, Thomas; Balakrishnan, Aneesh; Glorieux, Maximilien; Alexandrescu, Dan; Sterpone, Luca49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - DSN 2019 : Supplemental Volume : proceedings2019 / p. 35-41 : ill https://doi.org/10.1109/DSN-S.2019.00021

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Related publications 1

A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseks

306

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On-chip sensors data collection and analysis for SoC health managementShibin, Konstantin; Jenihhin, Maksim; Jutman, Artur; Devadze, Sergei; Tsertov, Anton2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)2023 / 6 p https://doi.org/10.1109/DFT59622.2023.10313562

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307

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On-line fault classification and handling in IEEE1687 based fault management system for complex SoCsShibin, Konstantin; Devadze, Sergei; Jutman, ArturLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 69-74 : ill https://doi.org/10.1109/LATW.2016.7483342

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308

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Operation of Single-Chip MOSFET and IGBT Devices after failure due to repetitive avalanche [Electronic resource]Blinov, Andrei; Norrga, Staffan; Tibola, GabrielEPE'15 ECCE Europe : 8-10 September 2015, Geneva, Switzerland : 17th European Conference on Power Electronics and Applications2015 / p. 1-9 : ill. [USB] http://dx.doi.org/10.1109/EPE.2015.7309190

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309

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Optimization of memory-constrained hybrid BIST for testing core-based systemsJervan, Gert; Kruus, Helena; Orasson, Elmet; Ubar, Raimund-JohannesProceedings of the IEEE 2nd International Symposium on Industrial Embedded Systems : SIES'2007 : Lisbon, Portugal, 4-6 July 20072007 / p. 71-77 https://ieeexplore.ieee.org/document/4297319

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310

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Overview of e-learning environment for web-based study of testing and diagnostics of digital systemsJutman, Artur; Ubar, Raimund-Johannes; Wuttke, Heinz-DietrichMicroelectronics education : proceedings of the 5th European Workshop on Microelectronics Education, held in Lausanne, Switzerland, April 15-16, 20042004 / p. 253-258 : ill https://link.springer.com/chapter/10.1007/978-1-4020-2651-5_41

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311

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Overview of e-learning environment for web-based study of testing and diagnostics of digital systemsJutman, Artur; Ubar, Raimund-Johannes; Wuttke, Heinz-Dietrich5th European Workshop on Microelectronics Education - EWME 2004, Lausanne, 20042004 / p. 173-176 https://link.springer.com/chapter/10.1007/978-1-4020-2651-5_41

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312

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Parallel critical path tracing fault simulationUbar, Raimund-Johannes39. Internationales Wissenschaftliches Kolloquium : 27.-30.09.1994. Bd. 1, Vortragsreihen1994 / S. 399-404

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313

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Parallel critical path tracing fault simulation in sequential circuitsKõusaar, Jaak; Ubar, Raimund-Johannes; Kostin, Sergei; Devadze, Sergei; Raik, JaanProceedings of 25th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS : MIXDES 2018 : Gdynia, Poland, June 21–23, 20182018 / p. 305-310 : ill https://doi.org/10.23919/MIXDES.2018.8436880

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314

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Parallel exact critical path tracing fault simulation with reduced memory requirementsDevadze, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Jutman, Artur4th International Conference on Design and Technology of Integrated Systems in Nanoscal Era : DTIS'09 : Cairo, Egypt, April 6-9, 20092009 / p. 155-160 : ill https://ieeexplore.ieee.org/document/4938046

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315

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Parallel fault analysis on structurally synthesized BDDsDevadze, Sergei; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 47-50 : ill

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316

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Parallel fault backtracing for calculation of fault coverageUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturProceedings of the ASP-DAC 2008 : [13th] Asia and South Pacific Design Automation Conference 2008 : January 21-24, 2008, COEX, Seoul, Korea2008 / p. 667-672 : ill https://www.researchgate.net/publication/221153650_Parallel_fault_backtracing_for_calculation_of_fault_coverage

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317

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Parallel fault backtracing for calculation of fault coverageUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur43rd International Conference on Microelectronics, Devices and Materials and the Workshop on Electronic Testing : September 12. - September 14.2007, Bled, Slovenia : MIDEM conference 2007 proceedings2007 / p. 165-170 : ill https://www.researchgate.net/publication/221153650_Parallel_fault_backtracing_for_calculation_of_fault_coverage

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318

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Parallel fault simulation in digital circuitsAarna, Margit; Raik, Jaan; Ubar, Raimund-JohannesProc. of 42nd International Scientific Conference of Riga Technical University2001 / p. 91-94

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319

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Parallel fault simulation in digital circuitsAarna, Margit; Raik, Jaan; Ubar, Raimund-JohannesScientific proceedings of Riga Technical University. 7. serija, Telecommunications and electronics2001 / p. 91-94 : ill

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320

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Parallel X-fault simulation with critical path tracing technique [Electronic resource]Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturDATE 10 : Design, Automation & Test in Europe : Dresden, Germany, 8-12 March, 20102010 / p. 879-884 [CD-ROM] https://www.researchgate.net/publication/221341788_Parallel_X-fault_simulation_with_critical_path_tracing_technique

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321

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Performance evaluation of additive manufacturing based test samples for studies of defects in electrical insulationShafiq, Muhammad; Taklaja, Paul; Kiitam, Ivar; Tiismus, Hans; Palu, Ivo; Kütt, Lauri2021 International Conference on Electrical, Computer and Energy Technologies (ICECET)2021 / 6 l https://doi.org/10.1109/ICECET52533.2021.9698476

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322

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Platform independent event correlation tool for network managementVaarandi, RistoNOMS 2002 : 2002 IEEE/IFIP Network Operations and Management Symposium "Management Solutions for the New Communications World" : proceedings2002 / p. 907-909 https://ieeexplore.ieee.org/document/1015640

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323

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PMU placement for fault line location using neural additive models—A global XAI techniquePerl, Michael; Sun, Zhenglong; Machlev, Ram; Belikov, Juri; Levy, Kfir Yehuda; Levron, YoashInternational journal of electrical power and energy systems2024 / art. 109573, 10 p. : ill https://doi.org/10.1016/j.ijepes.2023.109573 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

324

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Power quality issues in dispersed generation and smart gridsVaimann, Toomas; Niitsoo, Jaan; Kivipõld, Tanel; Lehtla, TõnuElektronika ir elektrotechnika = Electronics and electrical engineering2012 / p. 23-26 : ill https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=573c03a0753bcfce3929ba739ff032b16882acf5

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325

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Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environmentHe, Zhiyuan; Jervan, Gert; Peng, Zebo; Eles, PetruProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 83-86 : ill https://ieeexplore.ieee.org/document/1559782

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