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gate-level analysis (võtmesõna)

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Kirjeid leitud 3
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ekspordi kõik päringu tulemused (3)
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artikkel ajakirjas EST / artikkel ajakirjas ENG

Fast identification of true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Jürimägi, LembitMicroelectronics reliability2018 / p. 252-261 : ill https://doi.org/10.1016/j.microrel.2017.11.027 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

artikkel ajakirjas EST / artikkel ajakirjas ENG
2

artikkel kogumikus

Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176

artikkel kogumikus
3

artikkel kogumikus

A scalable technique to identify true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, JaanProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 152-157 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

artikkel kogumikus

Kirjeid leitud 3, kuvan 1 - 3

1. gate-level analysis
2. gate-level circuit abstraction
3. gate-level netlist
4. register transfer and gate level simulation
5. hierarchical two-level analysis
6. system-level analysis
7. logic level and high level BDDs
8. Field Programmable Gate Array (FPGA)
9. field programmable gate arrays
10. field-programmable gate array
11. Field-Programmable Gate Array (FPGA)
12. field-programmable gate arrays
13. field-programmable gate arrays (FPGA)
14. FPGA (field-programmable gate array)
15. GaTe
16. gate and register transfer levels
17. gate delay
18. gate driver
19. Gate Injection Transistor (GIT)
20. Golden gate assembly
21. insulated gate bipolar transistors
22. insulated gate-commutated thyristors
23. NBTI-critical gate
24. Opal Kelly ﬁeld programmable gate array (FPGA)
25. absolute sea level
26. airport level of service
27. arousal level
28. assurance level
29. behaviour level test generation
30. bi-level optimization
31. CO2 level in classrooms
32. CO2 level in classrooms and kindergartens
33. confidence level
34. country-level logistics
35. Cross-level Modeling of Faults in Digital Systems
36. customer compatibility level
37. deep level
38. deep level traps
39. determination of the CO2 level
40. determining the level of creatine
41. digitalisation level
42. distribution-level phasor measurement units (D-PMUs)
43. education level
44. exposure level
45. extreme penetration level of non synchronous generation
46. extreme sea-level prediction
47. extreme water level
48. graduate level
49. Hierarchical Multi-level Test Generation
50. high level DD (HLDD)
51. high level synthesis
52. high-level control fault model
53. high-level control faults
54. high-level decision diagram
55. high-level decision diagrams
56. high-level decision diagrams (HLDD) synthesis
57. High-level Decision Diagrams for Modeling Digital Systems
58. high-level expert group on AI
59. high-level fault coverage
60. high-level fault model
61. high-level fault simulation
62. high-level functional fault model
63. high-level synthesis
64. High-Level Synthesis (HLS)
65. high-level synthesis for test
66. high-level test data generation
67. improvement of safety level at enterprises
68. improvement of safety level at SMEs
69. lake level
70. level control
71. level crossing
72. Level of paranoia
73. level set
74. level(s) methodology
75. level-crossing ADC
76. level-crossing analog-to-digital converters
77. level-crossing analogue-to-digital converters (ADC)
78. logic level
79. lower trophic level models
80. low-level control system transportation
81. low-level fault redundancy
82. low-level radiation
83. Low-level RF EMF
84. macro-level industry influences
85. mean sea level
86. module level power electronics (MLPE)
87. module-level power electronics (MLPE)
88. multi-level governance
89. multi-level inverter
90. multi-level leadership
91. multi-level modeling
92. multi-level perspective
93. multi-level perspective of sustainability transitions
94. multi-level selection and processing environment
95. noise level
96. operational level (OL)
97. Price level
98. Process/Product Sigma Performance Level (PSPL)
99. PV module level power electronics
100. Register Transfer Level - RTL
101. register transfer level modeling decision diagams
102. register-transfer level
103. relative sea level
104. relative sea level changes
105. relative sea-level change
106. RH level
107. school-level policies
108. sea level
109. sea level forecasting
110. sea level prediction
111. sea level rise
112. sea level series
113. sea level trend
114. sea level: variations and mean
115. sea-level
116. sea-level changes
117. sea-level equation
118. Sea-level indicator
119. sea-level prediction
120. sea-level rise
121. sea-level trend
122. service-level agreements
123. seven-level multilevel
124. Sigma performance level
125. skin conductance level
126. software level TMR
127. steel-level bureaucracy
128. strategic level decision makers
129. system level
130. system level hazards
131. system level test
132. system planning level
133. system-level evaluation
134. task-level uninterrupted presence
135. three-level
136. three-level converter
137. three-level inverter
138. three-level neutral-point-clamped inverter
139. three-level NPC inverter
140. three-level T-type
141. three-level T-type inverter
142. three-level T-type quasi-impedance-source inverter (3L-T-type qZSI)
143. three-level voltage inverter
144. Tool Confidence Level
145. top-level domain
146. transaction-level modeling
147. treatment level
148. two-level inverter
149. undergraduate level
150. university level informatics education
151. water level
152. water level fluctuation
153. water level measurements
154. water level reconstruction
155. water-level changes
156. voltage level
157. voltage level optimisation
158. 3-level T-type inverter

1. Safety Gate

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