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gate-level analysis (võtmesõna)
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artikkel ajakirjas ENG
Fast identification of true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Jürimägi, Lembit
Microelectronics reliability
2018
/
p. 252-261 : ill
https://doi.org/10.1016/j.microrel.2017.11.027
Journal metrics at Scopus
Article at Scopus
Journal metrics at WOS
Article at WOS
artikkel ajakirjas EST
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artikkel ajakirjas ENG
2
artikkel kogumikus
Hierarchical timing-critical paths analysis in sequential circuits
Jürimägi, Lembit
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
;
Devadze, Sergei
;
Kostin, Sergei
2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain
2018
/
6 p. : ill
https://doi.org/10.1109/PATMOS.2018.8464176
artikkel kogumikus
3
artikkel kogumikus
A scalable technique to identify true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany
2017
/
p. 152-157 : ill
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553
artikkel kogumikus
Kirjeid leitud 3, kuvan
1 - 3
võtmesõna
145
1.
gate-level analysis
2.
gate-level circuit abstraction
3.
gate-level netlist
4.
register transfer and gate level simulation
5.
hierarchical two-level analysis
6.
system-level analysis
7.
logic level and high level BDDs
8.
Field Programmable Gate Array (FPGA)
9.
field programmable gate arrays
10.
field-programmable gate array
11.
Field-Programmable Gate Array (FPGA)
12.
field-programmable gate arrays
13.
field-programmable gate arrays (FPGA)
14.
FPGA (field-programmable gate array)
15.
GaTe
16.
gate and register transfer levels
17.
gate delay
18.
gate driver
19.
Gate Injection Transistor (GIT)
20.
Golden gate assembly
21.
insulated gate bipolar transistors
22.
insulated gate-commutated thyristors
23.
NBTI-critical gate
24.
Opal Kelly field programmable gate array (FPGA)
25.
absolute sea level
26.
airport level of service
27.
arousal level
28.
assurance level
29.
behaviour level test generation
30.
bi-level optimization
31.
CO2 level in classrooms
32.
CO2 level in classrooms and kindergartens
33.
confidence level
34.
country-level logistics
35.
Cross-level Modeling of Faults in Digital Systems
36.
customer compatibility level
37.
deep level
38.
deep level traps
39.
determination of the CO2 level
40.
determining the level of creatine
41.
digitalisation level
42.
distribution-level phasor measurement units (D-PMUs)
43.
exposure level
44.
extreme penetration level of non synchronous generation
45.
extreme water level
46.
graduate level
47.
Hierarchical Multi-level Test Generation
48.
high level DD (HLDD)
49.
high level synthesis
50.
high-level control fault model
51.
high-level control faults
52.
high-level decision diagram
53.
high-level decision diagrams
54.
high-level decision diagrams (HLDD) synthesis
55.
High-level Decision Diagrams for Modeling Digital Systems
56.
high-level expert group on AI
57.
high-level fault coverage
58.
high-level fault model
59.
high-level fault simulation
60.
high-level functional fault model
61.
high-level synthesis
62.
High-Level Synthesis (HLS)
63.
high-level synthesis for test
64.
high-level test data generation
65.
improvement of safety level at enterprises
66.
improvement of safety level at SMEs
67.
level control
68.
level set
69.
level(s) methodology
70.
level-crossing ADC
71.
level-crossing analog-to-digital converters
72.
level-crossing analogue-to-digital converters (ADC)
73.
logic level
74.
lower trophic level models
75.
low-level control system transportation
76.
low-level fault redundancy
77.
low-level radiation
78.
Low-level RF EMF
79.
macro-level industry influences
80.
mean sea level
81.
module level power electronics (MLPE)
82.
module-level power electronics (MLPE)
83.
multi-level governance
84.
multi-level inverter
85.
multi-level modeling
86.
multi-level perspective
87.
multi-level perspective of sustainability transitions
88.
multi-level selection and processing environment
89.
operational level (OL)
90.
Price level
91.
Process/Product Sigma Performance Level (PSPL)
92.
PV module level power electronics
93.
Register Transfer Level - RTL
94.
register transfer level modeling decision diagams
95.
register-transfer level
96.
relative sea level
97.
relative sea level changes
98.
relative sea-level change
99.
RH level
100.
school-level policies
101.
sea level
102.
sea level rise
103.
sea level series
104.
sea level trend
105.
sea level: variations and mean
106.
sea-level
107.
sea-level changes
108.
sea-level equation
109.
Sea-level indicator
110.
sea-level prediction
111.
sea-level rise
112.
sea-level trend
113.
service-level agreements
114.
seven-level multilevel
115.
skin conductance level
116.
software level TMR
117.
steel-level bureaucracy
118.
strategic level decision makers
119.
system level hazards
120.
system level test
121.
system planning level
122.
system-level evaluation
123.
task-level uninterrupted presence
124.
three-level
125.
three-level inverter
126.
three-level neutral-point-clamped inverter
127.
three-level NPC inverter
128.
three-level T-type
129.
three-level T-type inverter
130.
three-level T-type quasi-impedance-source inverter (3L-T-type qZSI)
131.
three-level voltage inverter
132.
Tool Confidence Level
133.
top-level domain
134.
transaction-level modeling
135.
treatment level
136.
two-level inverter
137.
undergraduate level
138.
water level
139.
water level fluctuation
140.
water level measurements
141.
water level reconstruction
142.
water-level changes
143.
voltage level
144.
voltage level optimisation
145.
3-level T-type inverter
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