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76

artikkel kogumikus

Fast test cost calculation for hybrid BIST in digital systemsOrasson, Elmet; Raidma, Rein; Ubar, Raimund-Johannes; Jervan, Gert; Peng, ZeboEuromicro Symposium on Digital Systems Design : [Architectures, Methods and Tools : DSD 2001] : September 4-6, 2001, Warsaw, Poland : proceedings2001 / p. 318-325 : ill https://www.semanticscholar.org/paper/Fast-test-cost-calculation-for-hybrid-BIST-in-Orasson-Raidma/5aafcda5a18c2aabf0ad20cac10af10727f3c58f

artikkel kogumikus

77

artikkel kogumikus

Fault collapsing with linear complexity in digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, ArturProceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010) : 30 May - 2 June 2010, Paris, France2010 / p. 653-656 : ill https://ieeexplore.ieee.org/document/5537504

artikkel kogumikus

78

artikkel kogumikus

Fault diagnosis in integrated circuits with BISTUbar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan; Evartson, Teet; Lensen, Harri10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings2007 / p. 604-610 : ill http://dx.doi.org/10.1109/DSD.2007.4341530

artikkel kogumikus

79

artikkel ajakirjas

Fault diagnosis in VLSI devicesUbar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering1995 / 1, p. 51-67

artikkel ajakirjas

80

artikkel ajakirjas

Fault effect reasoning in digital systems by topological view on low- and high-level decision diagramsUbar, Raimund-JohannesВестник Томского государственного университета. Управление, вычислительная техника и информатика2014 / p. 99-113 : ill http://journals.tsu.ru/informatics/&journal_page=archive&id=923&article_id=12107

artikkel ajakirjas

81

artikkel kogumikus

Fault simulation with parallel critical path tracing for combinational circuits using structurally synthesized BDDsDevadze, Sergei; Raik, Jaan; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 97-102 : ill

artikkel kogumikus

82

artikkel kogumikus

Faults and fault models for integrated circuits and systems [Electronic resource] : [slides]Ubar, Raimund-JohannesDesign and Test Technology for Dependable Hardware/Software Systems : DEDIS/DAAD Summer Academy : BTU Cottbus, Sept. 1st-12th, 20082008 / [64] p. : ill. [CD-ROM]

artikkel kogumikus

83

artikkel kogumikus

Finite state machines with datapath partitioning for low power synthesisSudnitsõn, AleksanderProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 163-168 : ill

artikkel kogumikus

84

artikkel kogumikus

Foreword to the 12th IEEE DDECS SymposiumPliva, Zdenek; Manhaeve, Hans; Renovell, Michel; Novak, Ondrej; Ubar, Raimund-Johannes; Drabkova, JindraProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 15-17, 2009, Liberec, Czech Republic2009 / p. iii http://dx.doi.org/10.1109/DDECS.2009.5012081

artikkel kogumikus

85

artikkel ajakirjas

From virtual characterization to test-chips : DFM analysis through pattern enumerationMartins, Mayler G.A.; Pagliarini, Samuel Nascimento; Isgenc, Mehmet Meric; Pileggi, LarryIEEE transactions on computer-aided design of integrated circuits and systems2020 / p. 520-532 https://doi.org//10.1109/TCAD.2018.2889772

artikkel ajakirjas

86

artikkel kogumikus

Fully-fusible convolutional neural networks for end-to-end fused architecture with FPGA implementationDadras, Iman; Seydi, Sakineh; Ahmadilivani, Mohammad Hasan; Raik, Jaan; Salehi, Mostafa E.2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)2023 / 5 p. https://doi.org/10.1109/ICECS58634.2023.10382831

artikkel kogumikus

87

artikkel kogumikus

Functional partitioning for register transfer level low power synthesisSudnitsõn, AleksanderECS'01 : proceedings of the 3rd Electronic Circuits and Systems Conference : September 5-7, 2001, Bratislava, Slovakia2001 / p. 73-76 : ill

artikkel kogumikus

88

artikkel kogumikus

Gate-level modelling of NBTI-induced delays under process variationsCopetti, Thiago; Cardoso Medeiros, Guilherme; Bolzani Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 75-80 : ill http://dx.doi.org/10.1109/LATW.2016.7483343

artikkel kogumikus

89

artikkel kogumikus

Generic interconnect BIST for Network-on-ChipJutman, Artur; Ubar, Raimund-Johannes; Raik, JaanDDECS : 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : April 13-16, 2005, Sopron, Hungary : proceedings2005 / p. 224-227 : ill

artikkel kogumikus

90

artikkel kogumikus

A global methodology for test program generation starting from high level specificationsStorojev, Sergei; Leveugle, Regis; Saucier, GabrieleBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 305-311: ill https://www.ester.ee/record=b2150914*est

artikkel kogumikus

91

dissertatsioon

Hardware realization of lattice-based post-quantum cryptography = Võrel põhinev post-kvant-krüptograafia riistvaraline realisatsioonImran, Malik2023 https://www.ester.ee/record=b5571216*est https://doi.org/10.23658/taltech.33/2023 https://digikogu.taltech.ee/et/Item/75aeb070-cb8b-4511-beaf-cbea3fca147d https://www.ester.ee/record=b5571216*est

dissertatsioon

Seotud publikatsioonid 6

92

raamat

Hardware/software co-design for programmable systems-on-chipSklyarov, Valery; Skliarova, Iouliia; Silva, João; Rjabov, Artjom; Sudnitsõn, Aleksander; Cardoso, Cláudia2014 http://www.ester.ee/record=b3087107*est

raamat

93

artikkel ajakirjas

A healthier chip?Ubar, Raimund-Johannes; Fridolin, Ivo; Meigas, Kalju; Min, MartPublic service review : European Union2010 / p. 132-133 : ill

artikkel ajakirjas

94

artikkel kogumikus

Hierarchical concurrent test generation for synchronous sequential circuitsUbar, Raimund-Johannes; Brik, MarinaProceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2000 : Gdynia, Poland, 15-17 June 20002000 / p. 533-538 : ill

artikkel kogumikus

95

artikkel kogumikus

High-level decision diagram based fault models for targeting FSMsRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi9th EUROMICRO Conference on Digital Systems Design : Architectures, Methods and Tools (DSD 2006) : 30 August 2006-1 September 2006, Cavtat near Dubrovnik, Croatia : proceedings2006 / p. 353-358 : ill http://dx.doi.org/10.1109/DSD.2006.60

artikkel kogumikus

96

artikkel kogumikus

High-Level Decision Diagram manipulations for code coverage analysisMinakova, Karina; Reinsalu, Uljana; Tšepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Ellervee, PeeterBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 207-210 : ill

artikkel kogumikus

97

artikkel kogumikus

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

artikkel kogumikus

98

artikkel kogumikus

High-level modeling and testing of multiple control faults in digital systemsJasnetski, Artjom; Oyeniran, Adeboye Stephen; Tšertov, Anton; Schölzel, Mario; Ubar, Raimund-JohannesFormal proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 20-22, 2016, Košice, Slovakia2016 / [6] p. : ill http://dx.doi.org/10.1109/DDECS.2016.7482445

artikkel kogumikus

99

artikkel ajakirjas EST / artikkel ajakirjas ENG

High-speed SABER key encapsulation mechanism in 65nm CMOSImran, Malik; Almeida, Felipe; Basso, Andrea; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoJournal of cryptographic engineering2023 / p. 461-471 : ill https://doi.org/10.1007/s13389-023-00316-2 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

artikkel ajakirjas EST / artikkel ajakirjas ENG

Seotud publikatsioonid 1

Hardware realization of lattice-based post-quantum cryptography = Võrel põhinev post-kvant-krüptograafia riistvaraline realisatsioon

100

artikkel ajalehes

Hiina võis sanktsioonide kiuste jõuda uue kiibitehnoloogiani [Võrguväljaanne]Einama, KaidoPostimees2022 Hiina võis sanktsioonide kiuste jõuda uue kiibitehnoloogiani

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