prindi

New fault models and self-test generation for microprocessors using High-Level Decision Diagrams

autor
Jasnetski, Artjom
Raik, Jaan
Tšertov, Anton
Ubar, Raimund-Johannes
vastutusandmed
Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
allikas
2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings
ilmumiskoht
Los Alamitos
kirjastus/väljaandja
IEEE Computer Society
ilmumisaasta
2015
leheküljed
p. 251-254 : ill
konverentsi nimetus, aeg
18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015, 22-24 April, 2015
konverentsi toimumispaik
Belgrade, Serbia
märksõna
mikroprotsessorid
testimine
tarkvara
otsustusdiagrammid
võtmesõna
microprocessor
software-based self-test (SBST)
test program generation
high-level decision diagrams
ISBN
978-1-4799-6780-3
märkused
Bibliogr.: 22 ref
TTÜ struktuuriüksus
arvutitehnika instituut
keel
inglise
Jasnetski, A., Raik, J., Tšertov, A., Ubar, R. New fault models and self-test generation for microprocessors using High-Level Decision Diagrams // 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings. Los Alamitos : IEEE Computer Society, 2015. p. 251-254 : ill.