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151

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Defect-oriented test generation and fault simulation in the environment of MOSCITOSchneider, Andre; Diener, Karl-Heinz; Gramatova, Elena; Fisherova, Maria; Ivask, Eero; Ubar, Raimund-Johannes; Pleskacz, Witold A.; Kuzmicz, W.BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 303-306 : ill

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152

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Defect-oriented test generation using probabilistic estimationCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 131-136 : ill

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153

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Defects, faults and fault modelsGramatova, Elena; Fisherova, Maria; Ubar, Raimund-Johannes; Pleskacz, Witold A.Handbook of testing electronic systems2005 / p. 26-96 : ill

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154

book article

DefSim - the defective ICPleskacz, Witold A.; Jutman, Artur; Ubar, Raimund-Johannes; Devadze, SergeiDATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 20072007 / p. s96 (2 p.)

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155

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DefSim: CMOS defects on chip for research and educationPleskacz, Witold A.; Borejko, Tomasz; Walkanis, A.; Stopjakova, Viera; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 74-79 : ill

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156

book article

DefSim: measurement environment for CMOS defectsBorejko, Tomasz; Jutman, Artur; Pleskacz, Witold A.; Ubar, Raimund-Johannes2006 25th International Conference on Microelectronics : Belgrade, Serbia and Montenegro, 14-17 May 2006 : proceedings. Volume 22006 / p. 679-682 https://ieeexplore.ieee.org/document/1651048

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157

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DefSim-based exercises for studying defects in CMOS gatesJutman, Artur; Pleskacz, Witold A.; Boiko, Nikolai; Ubar, Raimund-JohannesEWME 2006 proceedings : 6th International Workshop on Microelectronics Education : 8-9 June, 2006, Stockholm, Sweden2006 / p. 23-26 : ill

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158

book article

Delay testing of asynchronous NoC interconnectsBengtsson, Tomas; Jutman, Artur; Kumar, Shashi; Ubar, Raimund-JohannesProceedings of the 12th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2005 : Krakow, Poland, 22-25 June, 2005. Vol. 1 of 22005 / p. 419-424 : ill

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159

book article

Department of Computer EngineeringKeevallik, Andres; Ubar, Raimund-JohannesResearch activities / Tallinn Technical University1993 / p. 75-78 https://www.ester.ee/record=b1053754*est

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160

book article

Dependability evaluation in fault-tolerant systems with high-level decision diagramsUbar, Raimund-Johannes; Jervan, Gert; Raik, Jaan; Jenihhin, Maksim; Ellervee, PeeterComputer Science Meets Automation : 10-13 September 2007 : proceedings. Volume II2007 / p. 147-152 : ill https://www.db-thueringen.de/receive/dbt_mods_00008864

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161

book article

Description of digital objects with alternative graphs for test generation purposesUbar, Raimund-Johannes; Lohuaru, TõnuFault Tolerant Systems and Diagnostics : XI. International Conference ; Proceedings ; Suhl, June 6-9, 19881988 / p. [?]

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162

book

Design and test technology for dependable systems-on-chip2011 https://www.ester.ee/record=b4467408*est

book

163

journal article

Design error diagnosis in digital circuits with stuck-at fault modelJutman, Artur; Ubar, Raimund-JohannesMicroelectronics reliability2000 / 2, p. 307-320 : ill

journal article

164

book article

Design error diagnosis in digital circuits without error modelUbar, Raimund-Johannes; Borrione, DominiqueVLSI : systems on a chip : IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI'99) : December 1-4, 1999, Lisboa, Portugal1999 / p. 281-292 : ill

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165

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Design error diagnosis in scan-path designsUbar, Raimund-Johannes2nd IEEE Latin American Test Workshop : LATW 2001 : Cancun, Mexico, February 11-14, 2001 : digest of papers2001 / p. 162-168 : ill

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166

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Design error diagnosis using backtrace algorithm on decision diagramsRepinski, Urmas; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / p. 93-96

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167

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Design error diagnosis with re-synthesis in combinational circuitsUbar, Raimund-JohannesJournal of electronic testing : theory and applications2003 / 1, p. 73-82 : ill https://link.springer.com/article/10.1023/A:1021948013402

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168

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Design error localization in digital circuits by stuck-at fault test patternsJutman, Artur; Ubar, Raimund-Johannes[MIEL] 2000 : 22nd International Conference on Microelectronics : Niš, Yugoslavia, 14-17 May 2000 : proceedings. Volume 22000 / p. 723-726

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169

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Design technologies for system-on-chip : fault simulation in complex digital designsHahanov, V.; Ubar, Raimund-JohannesАвтоматизированные системы управления и приборы автоматики, 20032003 / p. 16-35

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170

journal article

Design-for-destability-based external test and diagnosis of mesh-like network- on-a-chipsRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesIET computers and digital techniques2009 / 5, p. 476-486 : ill http://dx.doi.org/10.1049/iet-cdt.2008.0096

journal article

171

book article

Deterministic defect-oriented test generation for combinational circuitsRaik, Jaan; Ubar, Raimund-Johannes; Sudbrock, Joachim; Kuzmicz, Wieslaw; Pleskacz, Witold A.LATW 2005 : 6th IEEE Latin-American Test Workshop : March 30 - April 2, 2005, Salvador, Bahia, Brazil : [digest of papers]2005 / p. 325-330 : ill

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172

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DfT for application of external test patterns in a Network-on-a-ChipGovind, Vineeth; Raik, Jaan; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 25-28 : ill

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173

book article

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysisHantson, Hanno; Repinski, Urmas; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-JohannesLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / [6 p.] : ill https://ieeexplore.ieee.org/document/6261234

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174

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Diagnostic modeling of digital systems with low- and high-level decision diagramsUbar, Raimund-JohannesLATW2013 : 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013 : [proceedings]2013 / [1] p

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175

book article

Diagnostic modeling of digital systems with multi-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, MaksimDesign and test technology for dependable systems-on-chip2011 / p. 92-118 : ill https://www.researchgate.net/publication/344994231_Diagnostic_Modeling_of_Digital_Systems_with_Multi-Level_Decision_Diagrams

book article

Ubar, Raimund-Johannes (author)

types of item

CV 61

author 57

name of the person 28

subject term 1