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151

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Defect-oriented fault simulation and test generation in digital circuitsKuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California2001 / p. 365-371

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152

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Defect-oriented library builder and hierarchical test generationCibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001 : Fourth International Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems : Györ, Hungary, April 18-20, 20012001 / p. 163-168 : ill

book article

153

journal article

Defect-oriented mixed-level fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaFacta Universitatis [Niš]. Series electronics and energetics2002 / 1, April, p. 123-136 : ill

journal article

154

book article

Defect-oriented modul-level fault diagnosis in digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanProceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 / p. 81-86

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155

book article

Defect-oriented test- and layout-generation for standard-cell ASIC designsSudbrock, Joachim; Raik, Jaan; Ubar, Raimund-Johannes; Kuzmicz, Wieslaw; Pleskacz, Witold A.Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 79-82 : ill

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156

book article

Defect-oriented test generation and fault simulation in the environment of MOSCITOSchneider, Andre; Diener, Karl-Heinz; Gramatova, Elena; Fisherova, Maria; Ivask, Eero; Ubar, Raimund-Johannes; Pleskacz, Witold A.; Kuzmicz, W.BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 303-306 : ill

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157

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Defect-oriented test generation using probabilistic estimationCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 131-136 : ill

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158

book article

Defects, faults and fault modelsGramatova, Elena; Fisherova, Maria; Ubar, Raimund-Johannes; Pleskacz, Witold A.Handbook of testing electronic systems2005 / p. 26-96 : ill

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159

book article

DefSim - the defective ICPleskacz, Witold A.; Jutman, Artur; Ubar, Raimund-Johannes; Devadze, SergeiDATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 20072007 / p. s96 (2 p.)

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160

book article

DefSim: CMOS defects on chip for research and educationPleskacz, Witold A.; Borejko, Tomasz; Walkanis, A.; Stopjakova, Viera; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 74-79 : ill

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161

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DefSim: measurement environment for CMOS defectsBorejko, Tomasz; Jutman, Artur; Pleskacz, Witold A.; Ubar, Raimund-Johannes2006 25th International Conference on Microelectronics : Belgrade, Serbia and Montenegro, 14-17 May 2006 : proceedings. Volume 22006 / p. 679-682 https://ieeexplore.ieee.org/document/1651048

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162

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DefSim-based exercises for studying defects in CMOS gatesJutman, Artur; Pleskacz, Witold A.; Boiko, Nikolai; Ubar, Raimund-JohannesEWME 2006 proceedings : 6th International Workshop on Microelectronics Education : 8-9 June, 2006, Stockholm, Sweden2006 / p. 23-26 : ill

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163

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Delay testing of asynchronous NoC interconnectsBengtsson, Tomas; Jutman, Artur; Kumar, Shashi; Ubar, Raimund-JohannesProceedings of the 12th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2005 : Krakow, Poland, 22-25 June, 2005. Vol. 1 of 22005 / p. 419-424 : ill

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164

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Department of Computer EngineeringKeevallik, Andres; Ubar, Raimund-JohannesResearch activities / Tallinn Technical University1993 / p. 75-78 https://www.ester.ee/record=b1053754*est

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165

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Dependability evaluation in fault-tolerant systems with high-level decision diagramsUbar, Raimund-Johannes; Jervan, Gert; Raik, Jaan; Jenihhin, Maksim; Ellervee, PeeterComputer Science Meets Automation : 10-13 September 2007 : proceedings. Volume II2007 / p. 147-152 : ill https://www.db-thueringen.de/receive/dbt_mods_00008864

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166

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Description of digital objects with alternative graphs for test generation purposesUbar, Raimund-Johannes; Lohuaru, TõnuFault Tolerant Systems and Diagnostics : XI. International Conference ; Proceedings ; Suhl, June 6-9, 19881988 / p. [?]

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167

book

Design and test technology for dependable systems-on-chip2011 https://www.ester.ee/record=b4467408*est

book

168

journal article

Design error diagnosis in digital circuits with stuck-at fault modelJutman, Artur; Ubar, Raimund-JohannesMicroelectronics reliability2000 / 2, p. 307-320 : ill

journal article

169

book article

Design error diagnosis in digital circuits without error modelUbar, Raimund-Johannes; Borrione, DominiqueVLSI : systems on a chip : IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI'99) : December 1-4, 1999, Lisboa, Portugal1999 / p. 281-292 : ill

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170

book article

Design error diagnosis in scan-path designsUbar, Raimund-Johannes2nd IEEE Latin American Test Workshop : LATW 2001 : Cancun, Mexico, February 11-14, 2001 : digest of papers2001 / p. 162-168 : ill

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171

book article

Design error diagnosis using backtrace algorithm on decision diagramsRepinski, Urmas; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / p. 93-96

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172

journal article

Design error diagnosis with re-synthesis in combinational circuitsUbar, Raimund-JohannesJournal of electronic testing : theory and applications2003 / 1, p. 73-82 : ill

journal article

173

book article

Design error localization in digital circuits by stuck-at fault test patternsJutman, Artur; Ubar, Raimund-Johannes[MIEL] 2000 : 22nd International Conference on Microelectronics : Niš, Yugoslavia, 14-17 May 2000 : proceedings. Volume 22000 / p. 723-726

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174

book article

Design technologies for system-on-chip : fault simulation in complex digital designsHahanov, V.; Ubar, Raimund-JohannesАвтоматизированные системы управления и приборы автоматики, 20032003 / p. 16-35

book article

175

journal article

Design-for-destability-based external test and diagnosis of mesh-like network- on-a-chipsRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesIET computers and digital techniques2009 / 5, p. 476-486 : ill http://dx.doi.org/10.1049/iet-cdt.2008.0096

journal article

Ubar, Raimund-Johannes (author)

types of item

author 55

CV 55

name of the person 27

subject term 1