Toggle navigation
Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles
Intranet
Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles
Intranet
Databases
Publications
Searching
My bookmarks
0
Jervan, Gert (TTÜ author)
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
Add criteria
Advanced search
filter
Clear
×
types of item
book
..
journal article
..
newspaper article
..
book article
..
dissertation
..
Open Access
..
Scientific publication
..
year
year of publication
Loading..
author
Loading..
TTÜ department
Loading..
subject term
Loading..
series
Loading..
name of the person
Loading..
keyword
Loading..
Clear
Number of records
185
Look more..
(3/34)
Export
export all inquiry results
(185)
Save TXT fail
Save PDF fail
print
Open for editing with marked entries
my bookmarks
display
Bibliographic view
Short view
sort
author ascending
author descending
year of publication ascending
year of publication descending
title ascending
title descending
76
book article
A hierarchical automatic test pattern generator based on using alternative graphs
Brik, Marina
;
Jervan, Gert
;
Markus, Antti
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Proceedings of the 4th International Workshop Mixed Design of Integrated Circuits and Systems : MIXDES'97 : Poznan, Poland, 12-14 June 1997
1997
/
p. 415-420
book article
77
book article
Hierarchical calculation of malicious faults for evaluating the fault-tolerance
Ubar, Raimund-Johannes
;
Devadze, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Jervan, Gert
;
Ellervee, Peeter
Proceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China
2008
/
p. 222-227 : ill
book article
78
book article
Hierarchical test generation for digital systems
Brik, Marina
;
Jervan, Gert
;
Markus, Antti
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Mixed design of integrated circuits and systems
1998
/
p. 131-136: ill
book article
79
book article
Hierarchical test generation with multi-level decision diagram models
Jervan, Gert
;
Markus, Antti
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Proceedings of the 7th IEEE North Atlantic Test Workshop, West Greenwich RI, USA, May 28-29, 1998
1998
/
p. 26-33
book article
80
book article
High-level synthesis and test in the MOSCITO-based virtual laboratory
Schneider, Andre
;
Diener, Karl-Heinz
;
Jervan, Gert
;
Peng, Z.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Hollstein, Thomas
;
Glesner, M.
BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia
2002
/
p. 287-290 : ill
book article
81
book article
High-level test synthesis with hierarchical test generation
Jervan, Gert
;
Eles, Petru
;
Peng, Zebo
;
Raik, Jaan
;
Ubar, Raimund-Johannes
17th NORCHIP Conference : Oslo, Norway, 8-9 November 1999 : proceedings
1999
/
p. 291-296
book article
82
newspaper article
Hirm masinate ees: tehisintellekti liiga kiirele arengule tõmmatakse pidurit
Strandberg, Marek
;
Einama, Kaido
Postimees
2023
/
lk. 5
https://dea.digar.ee/article/postimees/2023/03/31/3.11
Hirm masinate ees: tehisintellekti liiga kiirele arengule tahetakse tõmmata pidurit
newspaper article
83
journal article
Holistic approach for Fault-Tolerant Network-on-Chip based many-core systems [Online resource]
Azad, Siavoosh Payandeh
;
Niazmand, Behrad
;
Raik, Jaan
;
Jervan, Gert
;
Hollstein, Thomas
arXiv.org
2016
/
[8] p. : ill
journal article
84
book article
How to emulate Network-on-Chip?
Ellervee, Peeter
;
Jervan, Gert
Proceedings of the IEEE East-West Design & Test Workshop (EWDTW'06) : Sochi, Russia, September 15-19, 2006
2006
/
p. 282-286 : ill
book article
85
book article
A hybrid BIST architecture and its optimization for SoC testing
Jervan, Gert
;
Peng, Zebo
;
Ubar, Raimund-Johannes
;
Kruus, Helena
Proceedings of the 3rd International Symposium on Quality Electronic Design : ISQED 2002, March 18-21, 2002, San Jose, California
2002
/
p. 273-279 : ill
book article
86
journal article
Hybrid BIST methodology for testing core-based systems
Jervan, Gert
;
Ubar, Raimund-Johannes
;
Peng, Zebo
Proceedings of the Estonian Academy of Sciences. Engineering
2006
/
3-2, p. 300-322 : ill
journal article
87
book article
Hybrid BIST optimization for core-based systems with test pattern broadcasting
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Jervan, Gert
;
Peng, Zebo
DELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : 28-30 January 2004, Perth, Australia : proceedings
2004
/
p. 3-8 : ill
http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10057
book article
88
book article
Hybrid BIST optimization using reseeding and test set compaction
Jervan, Gert
;
Orasson, Elmet
;
Kruus, Helena
;
Ubar, Raimund-Johannes
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings
2007
/
p. 596-603 : ill
http://dx.doi.org/10.1109/DSD.2007.4341529
book article
89
journal article
Hybrid BIST optimization using reseeding and test set compaction
Jervan, Gert
;
Orasson, Elmet
;
Kruus, Helena
;
Ubar, Raimund-Johannes
Microprocessors and microsystems
2008
/
5/6, p. 254-262 : ill
journal article
90
book article
Hybrid BIST scheduling for NoC-based SoCs
Jervan, Gert
;
Shchenova, Tatjana
;
Ubar, Raimund-Johannes
Proceedings [of] 24th IEEE Norchip Conference : Linköping, Sweden, 20-21 November 2006
2006
/
p. 141-144 : ill
https://ieeexplore.ieee.org/document/4126966
book article
91
book article
Hybrid BIST time minimization for core-based systems with STUMPS architecture
Jervan, Gert
;
Eles, Petru
;
Peng, Zebo
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings
2003
/
p. 225-232 : ill
book article
92
book
Hybrid built-in self-test and test generation techniques for digital systems
Jervan, Gert
2005
https://www.ester.ee/record=b2177537*est
book
93
journal article
IKT haridus ülikoolides läbi TTÜ arvutitehnika instituudi vaateprisma
Kruus, Margus
;
Jervan, Gert
Arvutimaailm
2010
/
5, lk. 8-9 : fot
https://artiklid.elnet.ee/record=b2409375*est
journal article
94
book article
IMMizer : an innovative cost-effective method for minimizing assertion sets
Heidari Iman, Mohammad Reza
;
Raik, Jaan
;
Jervan, Gert
;
Ghasempouri, Tara
Proceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 2022
2022
/
p. 671 - 678
https://doi.org/10.1109/DSD57027.2022.00095
Article at Scopus
Article at WOS
book article
95
book article
An improved estimation methodology for hybrid BIST cost calculation
Jervan, Gert
;
Peng, Zebo
;
Ubar, Raimund-Johannes
;
Korelina, Olga
Proceedings [of] 22nd NORCHIP Conference : Oslo, Norway, 8-9 November 2004
2004
/
p. 297-300 : ill
book article
96
book article
An improved estimation technique for hybrid BIST test set generation
Jervan, Gert
;
Peng, Zebo
;
Ubar, Raimund-Johannes
;
Korelina, Olga
DDECS : 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : April 13-16, 2005, Sopron, Hungary : proceedings
2005
/
p. 182-185 : ill
book article
97
newspaper article
Innovaatiline tiiger või hääbuv väikeriik?
Jervan, Gert
Postimees
2022
/
Lk. 13
https://dea.digar.ee/article/postimees/2022/04/26/13.7
newspaper article
98
book article
Innovation and entrepreneurship in the computer systems curricula and Nordic Master School in innovative ICT
Jervan, Gert
;
Ellervee, Peeter
;
Kruus, Margus
22nd EAEEIE annual conference : June, 13-15, 2011, Maribor, Slovenija : conference book
2011
/
p. 9
book article
99
journal article
IT Akadeemia - hea näide, kuidas süstemaatiliselt koostööd teha
Jervan, Gert
Mente et Manu
2022
/
lk. 30-31 : portr
https://www.ester.ee/record=b1242496*est
journal article
100
book article
An iterative approach to test time minimization for parallel hybrid BIST architecture
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Jervan, Gert
;
Peng, Z.
5th IEEE Latin-American Test Workshop - LATW 2004 : Cartagena, Colombia, 2004 : digest of papers
2004
/
p. 98-103 : ill
book article
Number of records 185, displaying
76 - 100
previous
1
2
3
4
5
6
7
8
next
author
19
1.
Jervan, Gert
2.
Jervan, M.
3.
Jervan, Martin
4.
Allas, Gert Air
5.
Everaert, Gert
6.
Hankewitz, Gert D.
7.
Hütsi, Gert
8.
Jostov, Gert
9.
Jõgiste, Gert
10.
Kanter, Gert
11.
Kiiler, Gert
12.
Kulla, Gert
13.
Kääramees, Gert
14.
Lõhmus, Gert
15.
Preegel, Gert
16.
Tamberg, Gert
17.
Toming, Gert
18.
Valdek, Gert
19.
Velsberg, Gert
name of the person
9
1.
Jervan, Gert, 1974-
2.
Dorbek, Gert
3.
Hütsi, Gert
4.
Kanter, Gert
5.
Lõhmus, Gert
6.
Preegel, Gert
7.
Tamberg, Gert
8.
Toming, Gert
9.
Velsberg, Gert
CV
6
1.
Jervan, Gert 1974
2.
Hangelaid, Gert 1915-1944
3.
Kanter, Gert
4.
Lätt, Gert
5.
Tamberg, Gert 1972
6.
Toming, Gert 1984
×
vaste
starts with
ends with
containes
sort
Relevance
ascending
descending
year of publication
author
TTÜ department
subject term
series
name of the person
keyword
Otsing
Valikud
0
year of publication
AND
OR
NOT
author
AND
OR
NOT
TTÜ department
AND
OR
NOT
subject term
AND
OR
NOT
series
AND
OR
NOT
name of the person
AND
OR
NOT
keyword
AND
OR
NOT