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High-level modeling and testing of multiple control faults in digital systems (title)
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book article
High-level modeling and testing of multiple control faults in digital systems
Jasnetski, Artjom
;
Oyeniran, Adeboye Stephen
;
Tšertov, Anton
;
Schölzel, Mario
;
Ubar, Raimund-Johannes
Formal proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 20-22, 2016, Košice, Slovakia
2016
/
[6] p. : ill
http://dx.doi.org/10.1109/DDECS.2016.7482445
book article
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keyword
39
1.
Cross-level Modeling of Faults in Digital Systems
2.
High-level Decision Diagrams for Modeling Digital Systems
3.
high-level control faults
4.
high-level control fault model
5.
digital control systems
6.
Avoiding Mutual Masking of Multiple Faults
7.
multiple faults
8.
Test Group Generation for Detecting Multiple Faults
9.
logic level and high level BDDs
10.
multiple criteria modeling
11.
high impedance faults
12.
control faults
13.
multi-level modeling
14.
multiple-input multiple output system
15.
register transfer level modeling decision diagams
16.
Structural Decision Diagrams for Modeling Digital Circuits
17.
testing of digital devices
18.
transaction-level modeling
19.
high-frequency machine modeling
20.
level-crossing analog-to-digital converters
21.
level-crossing analogue-to-digital converters (ADC)
22.
high level DD (HLDD)
23.
high level of security
24.
high level synthesis
25.
high-level decision diagram
26.
high-level decision diagrams
27.
high-level decision diagrams (HLDD) synthesis
28.
high-level expert group on AI
29.
high-level fault coverage
30.
high-level fault model
31.
high-level fault simulation
32.
high-level functional fault model
33.
high-level synthesis
34.
High-Level Synthesis (HLS)
35.
high-level synthesis for test
36.
high-level test data generation
37.
modeling for control
38.
level control
39.
low-level control system transportation
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