Toggle navigation
Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles
Intranet
Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles
Intranet
Databases
Publications
Searching
My bookmarks
0
Representing gate-level SET faults by multiple SEU faults on RT-level (title)
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
Add criteria
Advanced search
filter
Clear
×
types of item
book
..
journal article
..
newspaper article
..
book article
..
dissertation
..
Open Access
..
Scientific publications
..
year
year of publication
Loading..
author
Loading..
TalTech department
Loading..
subject term
Loading..
series
Loading..
name of the person
Loading..
keyword
Loading..
Clear
Number of records
1
Look more..
(1/38)
Export
export all inquiry results
(1)
Save TXT fail
print
Open for editing with marked entries
my bookmarks
display
Bibliographic view
Short view
sort
author ascending
author descending
year of publication ascending
year of publication descending
title ascending
title descending
1
book article
Representing gate-level SET faults by multiple SEU faults on RT-level
Bagbaba, Ahmet Cagri
;
Jenihhin, Maksim
;
Ubar, Raimund-Johannes
;
Sauer, Christian
2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 13-15 July 2020 : proceedings
2020
/
art. 19889351, 6 p. : ill
https://doi.org/10.1109/IOLTS50870.2020.9159715
book article
Related publications
1
Methods to optimize functional safety assessment for automotive integrated circuits = Meetodid autotööstuse kiipide funktsionaalse ohutuse hindamise optimeerimiseks
Number of records 1, displaying
1 - 1
keyword
38
1.
Cross-level Modeling of Faults in Digital Systems
2.
high-level control faults
3.
Avoiding Mutual Masking of Multiple Faults
4.
multiple faults
5.
Test Group Generation for Detecting Multiple Faults
6.
gate-level analysis
7.
gate-level circuit abstraction
8.
gate-level netlist
9.
level set
10.
register transfer and gate level simulation
11.
logic level and high level BDDs
12.
arc faults
13.
broken rotor bar faults
14.
circuit faults
15.
classification of faults
16.
control faults
17.
faults
18.
faults classification
19.
faults in power system
20.
hard-to-detect faults
21.
high impedance faults
22.
indefinite faults
23.
inter-disk and inter-turn faults
24.
localization of faults
25.
motor faults
26.
non-robust and functional sensitization of delay faults
27.
power distribution faults
28.
power system faults
29.
rotor faults
30.
Safe Faults
31.
Single Stuck-at Faults
32.
stuck-at-faults
33.
tectonic faults
34.
terms-transient faults
35.
transient faults
36.
transition delay faults
37.
unknown faults
38.
untestable faults
×
match
starts with
ends with
containes
sort
Relevance
ascending
descending
year of publication
author
TalTech department
subject term
series
name of the person
keyword
Otsing
Valikud
0
year of publication
AND
OR
NOT
author
AND
OR
NOT
TalTech department
AND
OR
NOT
subject term
AND
OR
NOT
series
AND
OR
NOT
name of the person
AND
OR
NOT
keyword
AND
OR
NOT