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Analysis of a test method for delay faults in NoC interconnectsBengtsson, Tomas; Jutman, Artur; Kumar, Shashi; Ubar, Raimund-Johannes; Peng, ZeboProceedings of the IEEE East-West Design & Test Workshop (EWDTW'06) : Sochi, Russia, September 15-19, 20062006 / p. 42-46 : ill

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Challenges for future system-on-chip designHollstein, Thomas; Peng, Zebo; Ubar, Raimund-Johannes; Glesner, ManfredCircuit Paradigm in the 21st Century : ECCTD '01 : proceedings of the 15th European Conference on Circuit Theory and Design : Helsinki University of Technology, Finland, 28th-31st August 2001. Vol 32001 / p. 173-176

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Energy minimization for hybrid BIST in a system-on-chip test environmentUbar, Raimund-Johannes; Shchenova, Tatjana; Jervan, Gert; Peng, ZeboEuropean Test Symposium : ETS 2005 : 22-25 May 2005, Tallinn, Estonia : proceedings2005 / p. 2-7 : ill

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Fast test cost calculation for hybrid BIST in digital systemsOrasson, Elmet; Raidma, Rein; Ubar, Raimund-Johannes; Jervan, Gert; Peng, ZeboEuromicro Symposium on Digital Systems Design : [Architectures, Methods and Tools : DSD 2001] : September 4-6, 2001, Warsaw, Poland : proceedings2001 / p. 318-325 : ill https://www.semanticscholar.org/paper/Fast-test-cost-calculation-for-hybrid-BIST-in-Orasson-Raidma/5aafcda5a18c2aabf0ad20cac10af10727f3c58f

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High-level test synthesis with hierarchical test generationJervan, Gert; Eles, Petru; Peng, Zebo; Raik, Jaan; Ubar, Raimund-Johannes17th NORCHIP Conference : Oslo, Norway, 8-9 November 1999 : proceedings1999 / p. 291-296

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A hybrid BIST architecture and its optimization for SoC testingJervan, Gert; Peng, Zebo; Ubar, Raimund-Johannes; Kruus, HelenaProceedings of the 3rd International Symposium on Quality Electronic Design : ISQED 2002, March 18-21, 2002, San Jose, California2002 / p. 273-279 : ill https://ieeexplore.ieee.org/document/996750

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Hybrid BIST energy minimisation technique for system-on-chip testingJervan, Gert; Peng, Zebo; Shchenova, Tatjana; Ubar, Raimund-JohannesIEE proceedings computers & digital techniques2006 / 4, p. 208-216 : ill https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=5ae755d323ccba87f8ff886334e3dd6d33560874

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Hybrid BIST methodology for testing core-based systemsJervan, Gert; Ubar, Raimund-Johannes; Peng, ZeboProceedings of the Estonian Academy of Sciences. Engineering2006 / 3-2, p. 300-322 : ill

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Hybrid BIST optimization for core-based systems with test pattern broadcastingUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, ZeboDELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : 28-30 January 2004, Perth, Australia : proceedings2004 / p. 3-8 : ill https://ieeexplore.ieee.org/document/1409808

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Hybrid BIST time minimization for core-based systems with STUMPS architectureJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings2003 / p. 225-232 : ill https://ieeexplore.ieee.org/document/1250116

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An improved estimation methodology for hybrid BIST cost calculationJervan, Gert; Peng, Zebo; Ubar, Raimund-Johannes; Korelina, OlgaProceedings [of] 22nd NORCHIP Conference : Oslo, Norway, 8-9 November 20042004 / p. 297-300 : ill https://ieeexplore.ieee.org/document/1423882

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An improved estimation technique for hybrid BIST test set generationJervan, Gert; Peng, Zebo; Ubar, Raimund-Johannes; Korelina, OlgaDDECS : 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : April 13-16, 2005, Sopron, Hungary : proceedings2005 / p. 182-185 : ill

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Off-line testing of delay faults in NoC interconnectsBengtsson, Tomas; Jutman, Artur; Kumar, Shashi; Peng, Zebo; Ubar, Raimund-Johannes9th EUROMICRO Conference on Digital Systems Design : Architectures, Methods and Tools (DSD 2006) : 30 August 2006-1 September 2006, Cavtat near Dubrovnik, Croatia : proceedings2006 / p. 677-680 : ill http://dx.doi.org/10.1109/DSD.2006.72

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Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environmentHe, Zhiyuan; Jervan, Gert; Peng, Zebo; Eles, PetruProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 83-86 : ill

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Test cost minimization for hybrid BISTJervan, Gert; Peng, Zebo; Ubar, Raimund-JohannesIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 25-27 October 2000, Yamanashi, Japan : proceedings2000 / p. 283-298 : ill https://ieeexplore.ieee.org/abstract/document/887168

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Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocolsBengtsson, Tomas; Kumar, Shashi; Ubar, Raimund-Johannes; Jutman, Artur; Peng, ZeboIET computers and digital techniques2008 / 6, p. 445-460

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Test time minimization for hybrid BIST of core-based systemsJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, MaksimJournal of computer science and technology2006 / 6, p. 907-912 : ill https://link.springer.com/article/10.1007/s11390-006-0907-x

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Test time minimization for hybrid BIST of core-based systemsJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim12th Asian Test Symposium (ATS 2003) : 17-19 November 2003, Xian, China2003 / p. 318-325 : ill https://link.springer.com/article/10.1007/s11390-006-0907-x

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Test time minimization for hybrid BIST with test pattern broadcastingUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, ZeboIEEE NORCHIP 2003 : 21 Norchip Conference : Riga, Latvia, 10-11 November 2003 : proceedings2003 / p. 112-116 : ill https://www.ida.liu.se/labs/eslab/publications/pap/db/norchip03.pdf

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Peng, Zebo (author)

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author 11

CV 1