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book article

Fast and optimized task allocation method for low vertical link density 3-Dimensional Networks-on-Chip based many core systemsYing, Haoyuan; Hollstein, Thomas; Hofmann, KlausProceedings : Design, Automation & Test in Europe : Grenoble, France, March 18-22, 20132013 / p. 1777-1782 : ill

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journal article EST / journal article ENG

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systemsSklyarov, Valery; Skliarova, Iouliia; Rjabov, Artjom; Sudnitsõn, AleksanderProceedings of the Estonian Academy of Sciences2017 / p. 323-335 : ill https://doi.org/10.3176/proc.2017.3.07 http://www.ester.ee/record=b2355998*est Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

28

book article

A five step refactoring process : improving software design properlyPõld, Janari; Kalja, Ahto; Robal, TarmoDatabases and information systems : proceedings of the Eighth International Baltic Conference, Baltic DBAMPIS 2008 : Tallinn, June 2-5, 20082008 / p. 37-48 : ill

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journal article

FPGA-based accelerators for parallel data sortSklyarov, Valery; Skliarova, Iouliia; Sudnitsõn, AleksanderApplied computer systems2014 / p. 53-63 : ill

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30

journal article

Functional self-test of high-performance pipe-lined signal processing architecturesGorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, MartMicroprocessors and microsystems2015 / p. 909-918 : ill http://dx.doi.org/10.1016/j.micpro.2014.11.002

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31

book article

GSNoC — the comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systemsYing, Haoyuan; Hollstein, Thomas; Hofmann, KlausProceedings of the 2013 International Conference on High Performance Computing & Simulation (HPCS 2013) : July 1-July 5, 2013, Helsinki, Finland2013 / p. 217-223 : ill

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32

journal article EST / journal article ENG

Hardware trojan insertion in finalized layouts : from methodology to a silicon demonstrationPerez, Tiago Diadami; Pagliarini, Samuel NascimentoIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2023 / p. 2094-2107 https://doi.org/10.1109/TCAD.2022.3223846 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

Seotud publikatsioonid 1

Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline süntees

33

book article

Hardware/software co-design in extensible processing platforms for combinatorial search algorithmsSkliarova, Iouliia; Sklyarov, Valery; Rjabov, Artjom; Sudnitsõn, AleksanderMELECON 2014 : 2014 17th IEEE Mediterranean Electrotechnical Conference : 13-16 April 2014, Beirut, Lebanon2014 / p. 462-466 : ill

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34

book article

A hardware/software co-design reconfigurable network-on-chip FPGA emulation methodYing, Haoyuan; Hollstein, Thomas; Hofmann, Klaus2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) : Montpellier, France, 26-28 May, 20142014 / [8] p. : ill

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35

dissertation

High-level implementation-independent software-based self-test for RISC type microprocessors = Mikroprotsessorite tarkvarapõhine implementatsioonist mittesõltuv funktsionaalne enesekontrollOyeniran, Adeboye Stephen2020 https://digikogu.taltech.ee/et/Item/08a75fbb-3f71-4fe4-b3d0-3f37a9a5f36d

dissertation

36

book article

A hybrid BIST architecture and its optimization for SoC testingJervan, Gert; Peng, Zebo; Ubar, Raimund-Johannes; Kruus, HelenaProceedings of the 3rd International Symposium on Quality Electronic Design : ISQED 2002, March 18-21, 2002, San Jose, California2002 / p. 273-279 : ill https://ieeexplore.ieee.org/document/996750

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journal article

Hybrid BIST energy minimisation technique for system-on-chip testingJervan, Gert; Peng, Zebo; Shchenova, Tatjana; Ubar, Raimund-JohannesIEE proceedings computers & digital techniques2006 / 4, p. 208-216 : ill https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=5ae755d323ccba87f8ff886334e3dd6d33560874

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book article

Hybrid BIST scheduling for NoC-based SoCsJervan, Gert; Shchenova, Tatjana; Ubar, Raimund-JohannesProceedings [of] 24th IEEE Norchip Conference : Linköping, Sweden, 20-21 November 20062006 / p. 141-144 : ill https://ieeexplore.ieee.org/document/4126966

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39

book article

Hybrid BIST time minimization for core-based systems with STUMPS architectureJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings2003 / p. 225-232 : ill https://ieeexplore.ieee.org/document/1250116

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book article

Implementation of parallel operations over streams in extensible processing platformsSklyarov, Valery; Skliarova, Iouliia; Rjabov, Artjom; Sudnitsõn, Aleksander2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) : August 4-7, 2013, Columbus, Ohio : [proceedings]2013 / p. 852-855 : ill

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41

book

Infotehnoloogia. Sõnastik. Osa 11, TöötlusseadmedHanson, Vello; Agur, Ustus; Kalja, Ahto; Võhandu, Leo1999 https://www.ester.ee/record=b1211017*est

book

42

journal article

Jini tehnoloogiastKüngas, PeepArvutimaailm2000 / 8, lk. 45 https://artiklid.elnet.ee/record=b1004987*est

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43

journal article

JäljevahemäluToomsalu, ArvoA & A2002 / 2, lk. 8-19 : ill https://artiklid.elnet.ee/record=b1009485*est

journal article

44

book article

Latest trends in hardware security and privacyDi Natale, Giorgio; Regazzoni, Francesco; Albanese, Vincent; Lhermet, Frank; Loisel, Yann; Sensaoui, Abderrahmane; Pagliarini, Samuel Nascimento33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : ESA-ESRIN, Italy (On-line Virtual Event),October 19–21, 20202020 / 4 p. : ill https://doi.org/10.1109/DFT50435.2020.9250816

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45

book article

Localization of bugs in processor designs using zamiaCAD frameworkTšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions : Austin, USA, December 10–12, 20122012 / p. 1-6 https://ieeexplore.ieee.org/document/6519733

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46

journal article

Logic IP for low-cost IC design in advanced CMOS nodesIsgenc, Mehmet Meric; Martins, Mayler G.A.; Zackriya, V. Mohammed; Pagliarini, Samuel Nascimento; Pileggi, LarryIEEE Transactions on Very Large Scale Integration (VLSI) Systems2020 / p. 585-595 https://doi.org//10.1109/TVLSI.2019.2942825

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47

journal article

MASI-arhitektuuriga võrguprotsessorToomsalu, ArvoA & A2004 / 3, lk. 7-18

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48

book article EST / book article ENG

Memristive device based circuits for computation-in-memory architecturesLebdeh, Muath Abu; Reinsalu, Uljana; Nguyen, Hoang Anh Du; Wong, Stephan; Hamdioui, Said2019 IEEE International Symposium on Circuits and Systems (ISCAS) : proceedings2019 / 5 p. : ill https://doi.org/10.1109/ISCAS.2019.8702542 Conference proceedings at Scopus Article at Scopus Article at WOS

book article EST / book article ENG

49

book

Mikroprotsessorsüsteemid : kursuseprojekti juhendmaterjalToomsalu, Arvo1998 https://www.ester.ee/record=b1061287*est

book

50

journal article

Model Driven ArchitectureLeis, PaulA & A2004 / 1, lk. 13-20 : ill https://artiklid.elnet.ee/record=b1014997*est

journal article

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