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CAC 2.0 : a corrupt and correct logic locking technique resilient to structural analysis attacksAksoy, Levent; Yasin, Muhammad; Pagliarini, Samuel2024 IEEE 25th Latin American Test Symposium (LATS) : 9-12 April 2024 (2024)2024 https://doi.org/10.1109/LATS62223.2024.10534592 Article at Scopus

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A CAD system for teaching digital testUbar, Raimund-Johannes; Ivask, Eero; Paomets, Priidu; Raik, JaanBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 369-372: ill

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Cal-Techist PocketronicuniToomsalu, ArvoA & A2005 / 4, lk. 9-12 https://artiklid.elnet.ee/record=b1018130*est

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Capacitance measurement with MSP430 microcontrollersMärtens, Olev; Pille, Siim; Reidla, MarkoEDERC2014 : proceedings of the 6th European Embedded Design in Education and Research Conference, 11-12 September 2014, Milan, Italy2014 / p. 260-263 : ill

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Capacitance-to-digital : a single chip detector for capillary electrophoresisDrevinskas, Tomas; Kaljurand, Mihkel; Maruška, AudriusElectrophoresis2014 / p. 2401-2407 : ill

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Chip-to-Chip authentication method based on SRAM PUF and public key cryptographyKarageorgos, Ioannis; Isgenc, Mehmet Meric; Pagliarini, Samuel Nascimento; Pileggi, LarryJournal of hardware and systems security2019 / p. 382–396 : ill https://doi.org/10.1007/s41635-019-00080-y

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Circuit simulation program oriented physical modeling of integrated circuit elementsRang, Toomas; Tarnay, K.; Szekely, V.Periodica polytechnica. Electrical engineering = Электротехника1980 / p. 37-45 https://www.ester.ee/record=b1198855*est

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Code coverage analysis for concurrent programming languages using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesProceedings of the 12th European Workshop on Dependable Computing : EWDC 2009 : Toulouse, France, May 14-15, 20092009 / [4] p. : ill https://hal.archives-ouvertes.fr/hal-00381559

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Combining symbolic techniques with topological approach in test generationUbar, Raimund-JohannesProceedings of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 19961996 / p. 377-382

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A compact 16*16 CMOS cellular neural network chipPaasio, Ari; Dawidziuk, Adam; Porra, VeikkoBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 171-174: ill

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Compact avalanche transistor model for circuit simulation of Bi and BiCMOS cellsBubennikov, Alexander N.; Kobosev, Gennady; Kozhuhov, D.; Uchenov, A.BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 21994 / p. 523-527: ill https://www.ester.ee/record=b2150914*est

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Computational kernel extraction for synthesis of power-managed sequential componentsSudnitsõn, AleksanderProceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems : ICECS'2002, Dubrovnik, Croatia2002 / p. 749-752 https://ieeexplore.ieee.org/abstract/document/1046277

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Construction of the tests of combinational circuit failures by analyzing the orthogonal disjunctive normal forms represented by the alternative graphsMatrosova, A.Yu.; Pleshkov, A.G.; Ubar, Raimund-JohannesAutomation and remote control2005 / p. 313-327 : ill http://dx.doi.org/10.1007/s10513-005-0054-9

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Decision diagrams - from a mathematical notion to engineering applicationsStankovic, Radomir S.; Ubar, Raimund-Johannes; Astola, JaakkoFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 281-301 : ill http://dx.doi.org/10.2298/FUEE1103281S

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Defect-oriented test- and layout-generation for standard-cell ASIC designsSudbrock, Joachim; Raik, Jaan; Ubar, Raimund-Johannes; Kuzmicz, Wieslaw; Pleskacz, Witold A.Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 79-82 : ill https://ieeexplore.ieee.org/document/1559781

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Defect-oriented test generation using probabilistic estimationCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 131-136 : ill

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DefSim - the defective ICPleskacz, Witold A.; Jutman, Artur; Ubar, Raimund-Johannes; Devadze, SergeiDATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 20072007 / p. s96 (2 p.)

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DefSim: CMOS defects on chip for research and educationPleskacz, Witold A.; Borejko, Tomasz; Walkanis, A.; Stopjakova, Viera; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 74-79 : ill

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DefSim: measurement environment for CMOS defectsBorejko, Tomasz; Jutman, Artur; Pleskacz, Witold A.; Ubar, Raimund-Johannes2006 25th International Conference on Microelectronics : Belgrade, Serbia and Montenegro, 14-17 May 2006 : proceedings. Volume 22006 / p. 679-682 https://ieeexplore.ieee.org/document/1651048

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Design and optimization of super-speed CMOS/CBiCMOS circuits based on TCAD and time-logical simulatorBubennikov, Alexander; Blinnik, Semen B.BEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 473-474: ill

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Design and test technology for dependable systems-on-chip2011 https://www.ester.ee/record=b4467408*est

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Design of a generalized fractional-order PID controller using operational amplifiersGonzalez, Emmanuel A.; Alimisis, Vassilis; Psychalinos, Costas; Tepljakov, Aleksei2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS), Bordeaux, France, December 9–12, 20182018 / p. 253-256 : ill http://dx.doi.org/10.1109/ICECS.2018.8617954

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Design space exploration and optimisation for NoC-based timing sensitive systemsTagel, Mihkel; Ellervee, Peeter; Jervan, GertBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 177-180 : ill

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Design space exploration and optimisation for NoC-based timing sensitive systemsTagel, Mihkel; Ellervee, Peeter; Jervan, GertInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 117-120 : ill

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Design-for-destability-based external test and diagnosis of mesh-like network- on-a-chipsRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesIET computers and digital techniques2009 / 5, p. 476-486 : ill http://dx.doi.org/10.1049/iet-cdt.2008.0096

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