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A new evolutionary-technique-based approach to optimize pseudo-random TPG for logic BISTJutman, Artur; Aleksejev, Jevgeni; Ubar, Raimund-JohannesMEET/MARIND'2002 : proceedings of First International Congress on Mechanical and Electrical Engineering and Technology and Fourth International Conference on Marine Industry, 07-11 October 2002, Varna Bulgaria. Volume 12002 / p. 247-252 : ill

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A scalable static test set compaction method for sequential circuitsAleksejev, Igor; Raik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesProceedings of the 9th IEEE Latin-American Test Workshop : LATW2008 : February 17-20, 2008, Puebla, Mexico2008 / p. 87-92 : ill

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A tool for advanced learning of LFSR-based testing principlesJutman, Artur; Tšertov, Anton; Ubar, Raimund-JohannesBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 175-178 : ill

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A tool for teaching pseudo-random TPG principlesJutman, Artur; Tšertov, Anton; Ubar, Raimund-JohannesProceedings of the 17th EAEEIE Annual Conference on Innovation in Education for Electrical and Information Engineering : Craiova, Romania, June 1st-3rd, 20062006 / p. 182-187 : ill

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An educational environment for digital testing : hardware, tools, and web-based runtime platformJutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes; Vislogubov, VladislavProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 412-419 : ill https://www.researchgate.net/profile/Artur-Jutman/publication/220880167_An_Educational_Environment_for_Digital_Testing_Hardware_Tools_and_Web-Based_Runtime_Platform/links/02e7e53c3c71b0b2a7000000/An-Educational-Environment-for-Digital-Testing-Hardware-Tools-and-Web-Based-Runtime-Platform.pdf

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Analysis of a test method for delay faults in NoC interconnectsBengtsson, Tomas; Jutman, Artur; Kumar, Shashi; Ubar, Raimund-Johannes; Peng, ZeboProceedings of the IEEE East-West Design & Test Workshop (EWDTW'06) : Sochi, Russia, September 15-19, 20062006 / p. 42-46 : ill

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Applets for learning digital design and test [Electronic resource]Ubar, Raimund-Johannes; Jutman, Artur; Kruus, Margus; Wuttke, Heinz-Dietrich1st International Conference on Interactive Mobile and Computer Aided Learning (IMCL2006) : Amman, Jordan, April 19-21, 20062006 / p. 1-4 : ill. [CD-ROM]

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Application of sequential test set compaction to LFSR reseedingAleksejev, Igor; Jutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes26th Norchip Conference : Tallinn, Estonia, 17-18 November 2008 : formal proceedings2008 / p. 102-107 : ill http://dx.doi.org/10.1109/NORCHP.2008.4738292

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journal article

Application of structurally synthesized binary decision diagrams for timing simulation of digital circuitsJutman, Artur; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering2001 / 4, p. 269-288 : ill

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Assessment of student's design results in e-learning-scenarios [Electronic resource]Wuttke, Heinz-Dietrich; Ubar, Raimund-Johannes; Henke, Karsten; Jutman, Artur8th International Conference on Technology Based Higher Education and Training : 10th to 13th July, 2007, KKR Hotel Kumamoto, Kumamoto, Japan : [proceedings]2007 / [6] p. [CD-ROM]

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Asynchronous e-learning resources for hardware design issuesJutman, Artur; Sudnitsõn, Aleksander; Ubar, Raimund-Johannes; Wuttke, Heinz-DietrichProceedings of the International Conference on Computer Systems and Technologies (e-learning) : CompSysTech'04 : Rousse, Bulgaria, 17-18 June2004 / p. IV.11-1 - IV.11-6 : ill https://www.researchgate.net/publication/234797327_Asynchronous_e-learning_resources_for_hardware_design_issues

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Asynchronous fault detection in IEEE P1687 instrument networkShibin, Konstantin; Devadze, Sergei; Jutman, ArturIEEE 23rd North Atlantic Test Workshop : 14-16 May 2014, Binghampton, New York : proceedings2014 / p. 73-78 : ill

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At-speed on-chip diagnosis of board-level interconnect faultsJutman, ArturNinth IEEE European Test Symposium : ETS 2004 : 23-26 May 2004, Corsica, France : proceedings2004 / p. 2-7 : ill https://www.researchgate.net/publication/4098807_At-speed_on-chip_diagnosis_of_board-level_interconnect_faults

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Automatic SoC level test path synthesis based on partial functional modelsTšertov, Anton; Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei2011 Asian Test Symposium (ATS) : New Delhi, India2011 / p. 532-538 https://ieeexplore.ieee.org/document/6114730

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Automation of testing beyond the SoCsTšertov, Anton; Jutman, Artur; Devadze, SergeiInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 29-32 : ill

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BASTION : board and SoC test instrumentation for ageing and no failure foundJutman, Artur; Lotz, Christophe; Larsson, Erik; Sonza Reorda, Matteo; Jenihhin, Maksim; Raik, JaanProceedings of the 2017 Design, Automation & Test in Europe (DATE) : 27-31 March 2017, Swisstech, Lausanne, Switzerland2017 / p. 115-120 : ill https://doi.org/10.23919/DATE.2017.7926968

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BIST analyzer : a training platform for SoC testing [Electronic resource]Jutman, Artur; Tšertov, Anton; Tšepurov, Anton; Aleksejev, Igor; Ubar, Raimund-Johannes; Wuttke, Heinz-Dietrich37th Annual Frontiers in Education Conference : Global Engineering : Knowledge Without Borders, Opportunities Without Passports : Milwaukee, Wisconsin, October 10-13, 20072007 / p. S3H-8-S3H-13 : ill. [CD-ROM] http://dx.doi.org/10.1109/FIE.2007.4418125

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Bringing research issues into lab scenarios on the example of SoC testing [Electronic resource]Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei; Wuttke, Heinz-DietrichInternational Conference on Engineering Education - ICEE 2007 : September 3-7, 2007, Coimbra, Portugal2007 / [7] p. : ill. [CD-ROM] http://icee2007.dei.uc.pt/proceedings/papers/429.pdf

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Calculation of LFSR seed and polynomial pair for BIST applicationsJutman, Artur; Tšertov, Anton; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 105-108 : ill

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Calculation of LFSR seed and polynomial pair for BIST applications [Electronic resource]Jutman, Artur; Tšertov, Anton; Ubar, Raimund-Johannes2008 IEEE Design and Diagnostics of Electronic Circuits and Systems : Bratislava, Slovakia, April 16-18, 20082008 / p. 275-279 : ill. [CD-ROM] https://ieeexplore.ieee.org/abstract/document/4538801

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CMOS defects analysis using DefSim measurement environmentPleskacz, Witold A.; Borejko, Tomasz; Walkanis, A.; Stopjakova, Viera; Jutman, Artur; Ubar, Raimund-JohannesInformal Digest of Papers : Eleventh IEEE European Test Symposium : ETS 2006 : 21-24 May 2006, Southampton, United Kingdom2006 / p. 241-246 : ill

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CMS drift tubes sector collector relocation phase 1 upgrade [Electronic resource]Bedoya, C. F.; Jutman, Artur; Shibin, Konstantin; Devadze, Sergei2015 http://cms.cern.ch/iCMS/jsp/openfile.jsp?type=DN&year=2015&files=DN2015_011.pdf

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DefSim - the defective ICPleskacz, Witold A.; Jutman, Artur; Ubar, Raimund-Johannes; Devadze, SergeiDATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 20072007 / p. s96 (2 p.)

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DefSim: a remote laboratory for studying physical defects in CMOS digital circuitsPleskacz, Witold A.; Stopjakova, Viera; Borejko, Tomasz; Jutman, Artur; Walkanis, AndrzejIEEE transactions on industrial electronics2008 / 6, p. 2405-2415 : ill https://www.researchgate.net/publication/3219964_DefSim_A_Remote_Laboratory_for_Studying_Physical_Defects_in_CMOS_Digital_Circuits

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DefSim: CMOS defects on chip for research and educationPleskacz, Witold A.; Borejko, Tomasz; Walkanis, A.; Stopjakova, Viera; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 74-79 : ill

book article

Jutman, Artur (author)

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