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book article

A proposal for optimisation of low-powered FSM testingBrik, Marina; Fomina, Jelena; Ubar, Raimund-JohannesProceedings of IEEE East-West Design & Test Workshop (EWDTW'05) : Odessa, Ukraine, September 15-19, 20052005 / p. 15-20

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book article

An improved test generation approach for sequential circuits using decision diagramsBrik, Marina; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 155-158: ill

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book article

A benchmark suite for evaluating the efficiency of test toolsKruus, Helena; Ubar, Raimund-Johannes; Ellervee, Peeter; Gorev, Maksim; Pesonen, Vadim; Devadze, Sergei; Orasson, Elmet; Brik, Marina; Min, Mart; Annus, Paul; Kruus, Margus; Meigas, KaljuBEC 2012 : 2012 13th Biennial Baltic Electronics Conference : proceedings of the 13th Biennial Baltic Electronics Conference : October 3-5, 2012, Tallinn, Estonia2012 / p. 85-88 : ill

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book

Combinatorial algorithms of discrete mathematicsZakrevskij, Arkadij; Pottosin, Yu.; Cheremisinova, L.2008 http://www.ester.ee/record=b2350865*est

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journal article

Defect-oriented mixed-level fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaFacta Universitatis [Niš]. Series electronics and energetics2002 / 1, April, p. 123-136 : ill

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book article

Diagnostic modeling of microprocessors with high-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Brik, Marina; Istenberg, Martin; Wuttke, Heinz-DietrichBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 147-150 : ill

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7

book article

E-learning of digital logicRobal, Tarmo; Brik, Marina; Aarna, MargitEWME 2006 proceedings : 6th International Workshop on Microelectronics Education : 8-9 June, 2006, Stockholm, Sweden2006 / p. 120-123 : ill

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book article

Functional test generation for finite state machinesUbar, Raimund-Johannes; Brik, Marina; Jutman, Artur; Raik, Jaan; Bengtsson, Tomas; Kumar, ShashiBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 205-208 : ill

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9

book article

GA-based test generation for sequential circuitsBrik, Marina; Raik, Jaan; Ubar, Raimund-Johannes; Ivask, EeroProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 30-34

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10

book article

Hardware close programming for freshmenKruus, Helena; Brik, Marina; Kruus, Margus; Ruberg, Priit; Viies, Vladimir; Ellervee, Peeter10th European Workshop on Microelectronics Education : EWME 2014 : May 14-16, 2014, Tallinn, Estonia2014 / p. 93-96 : ill

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book article

A hierarchical automatic test pattern generator based on using alternative graphsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 4th International Workshop Mixed Design of Integrated Circuits and Systems : MIXDES'97 : Poznan, Poland, 12-14 June 19971997 / p. 415-420

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12

book article

Hierarchical concurrent test generation for synchronous sequential circuitsUbar, Raimund-Johannes; Brik, MarinaProceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2000 : Gdynia, Poland, 15-17 June 20002000 / p. 533-538 : ill

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book article

Hierarchical fault simulation for finite state machinesBrik, Marina; Raik, Jaan; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 145-148 : ill

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14

book article

Hierarchical fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaInternational Symposium on Signals, Circuits and Systems : SCS 2001 : July 10-11, 2001, Iasi, Romania : proceedings2001 / p. 181-184 : ill

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15

journal article

Hierarchical physical defect reasoning in digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Brik, MarinaEstonian journal of engineering2011 / 3, p. 185-200

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book article

Hierarchical test generation for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesMixed design of integrated circuits and systems1998 / p. 131-136: ill https://link.springer.com/chapter/10.1007/978-1-4615-5651-0_20

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book article

Hierarchical test generation for finite state machinesBrik, Marina; Ubar, Raimund-JohannesBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 319-324: ill

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18

book article

High level fault modeling in digital systemsUbar, Raimund-Johannes; Aarna, Margit; Brik, Marina; Raik, JaanSynergies between Information and Automation : 49. Internationales Wissenschaftliches Kolloquium, 27.-30.9.2004, Technische Universität Ilmenau, Germany. Volume 22004 / p. 486-491

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dissertation

Investigation and development of test generation methods for control part of digital systemsBrik, Marina2002 http://www.ester.ee/record=b1688656*est

dissertation

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book article

Mixed-level defect simulation in data-paths of digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, Marina23rd International Conference on Microelectronics : MIEL 2002, Niš, Yugoslavia, 12-15 May 2002 : proceedings. Volume 22002 / p. 617-620 : ill https://ieeexplore.ieee.org/document/1003333

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journal article

Mixed-level test generator for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering1997 / 4, p. 271-282 : ill

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book article

Multi-level fault simulation of digital systems on decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaThe First IEEE International Workshop on Electronic Design, Test and Applications : DELTA 2002, 29-31 January 2002, Christchurch, New Zealand : proceedings2002 / p. 86-91 : ill

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book article

Multi-level test generation and fault diagnosis for finite state machinesUbar, Raimund-Johannes; Brik, MarinaDependable computing : proceedings / EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 19961996 / p. 264-281: ill

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book article

A new approach to state encoding of low power FSMFomina, Jelena; Brik, Marina; Sudnitsõn, Aleksander; Vasiliev, RomanProceedings of IEEE East-West Design & Test Workshop : EWDTW'05 : Ukraine2005 / p. 21-26

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book article

On using genetic algorithm for test generationBrik, Marina; Raik, Jaan; Ubar, Raimund-Johannes; Ivask, EeroBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 233-236 : ill

book article

Brik, Marina (author)

types of item

author 67

CV 23

name of the person 11