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276

book article

Feasibility of structurally synthesized BDD models for test generationRaik, Jaan; Ubar, Raimund-JohannesProceedings of the IEEE European Test Workshop, Barcelona, Spain, May 27-29, 19981998 / p. 145-146

book article

277

book

Fehler in Automaten1989 http://www.ester.ee/record=b2015320*est

book

278

journal article

Fehlerbestimmung in kombinatorischen Scaltungen durch Lösung der Booleschen DifferentialgleichungenUbar, Raimund-JohannesNachrichtentechnik, Elektronik : technisch-wissenschaftlishe Zeitschrift für die gesamte elektronische Nachrichtentechnik1978 / p. 330-334 : ill https://www.ester.ee/record=b1550811*est

journal article

279

book article

ForewordUbar, Raimund-Johannes; Prinetto, Paolo; Al-Hashimi, BashirInformal Digest of Papers : 10 IEEE European Test Symposium : Tallinn, Estonia, May 22-25, 20052005 / p. III

book article

280

book article

Foreword to the 12th IEEE DDECS SymposiumPliva, Zdenek; Manhaeve, Hans; Renovell, Michel; Novak, Ondrej; Ubar, Raimund-Johannes; Drabkova, JindraProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 15-17, 2009, Liberec, Czech Republic2009 / p. iii http://dx.doi.org/10.1109/DDECS.2009.5012081

book article

281

dissertation

Formal verification and error correction on high-level decision diagrams = Formaalne verifitseerimine ja vigade parandamine kõrgtasemelistel otsustusdiagrammidelKarputkin, Anton2012

dissertation

282

book article

FPGA based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings [of] 22nd NORCHIP Conference : Oslo, Norway, 8-9 November 20042004 / p. 59-62 https://ieeexplore.ieee.org/abstract/document/1423822

book article

283

book article

FPGA design flow with automated test generationElst, G.; Diener, Karl-Heinz; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesProc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems : Potsdam, 19991999 / p. 120-123

book article

284

journal article

FPGA-based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tammemäe, Kalle; Ubar, Raimund-JohannesIET computers and digital techniques2007 / 2, p. 70-76 : ill https://ieeexplore.ieee.org/abstract/document/1423822

journal article

285

book article

From online fault detection to fault management in network-on-chips : a ground-up approachAzad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Nevin, George; Oyeniran, Adeboye Stephen; Putkaradze, Tsotne; Apneet Kaur; Raik, Jaan; Jervan, Gert; Ubar, Raimund-Johannes; Hollstein, ThomasProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 48-53 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

book article

286

book article

FTGEN - система генерирования функциональных тестовUbar, Raimund-Johannes; Dušina, Julia; Zaugarov, Viktor; Крупнова Е.; Storožev, SergeiProceedings of CAD-93 : new information technologies for science, education and business, Yalta, May 4-13, 19931993 / p. 123-125

book article

287

book article

Functional built-in self-test for processor cores in SoCUbar, Raimund-Johannes; Indus, Viljar; Kalmend, Oliver; Evartson, Teet; Orasson, Elmet30th IEEE NORCHIP Conference : Copenhagen, Denmark, November 12-14, 20122012 / p. 1-4 : ill

book article

288

book article

Functional level controllability analysis for digital circuitsUbar, Raimund-Johannes; Kuchcinski, KtzysztofProc. of the Design Automation Conference, Kaunas, Lithuania, June 1-4, 19921992 / p. 13-21

book article

289

book article

Functional level test set generation methodsUbar, Raimund-JohannesProceedings of the 12th Conference on Fault-Tolerant Systems and Diagnostics, Prague, Czechoslovakia, September, 19891989 / p. 46-55

book article

290

book article

Functional level testability analysis for digital circuitsUbar, Raimund-Johannes; Kuchcinski, KtzysztofETC '93 : European Test Conference, Rotterdam, The Netherlands, April 19-22, 19931993 / p. 545-546

book article

291

book

Functional level testability analysis for digital circuitsUbar, Raimund-Johannes1992

book

292

journal article

Functional self-test of high-performance pipe-lined signal processing architecturesGorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, MartMicroprocessors and microsystems2015 / p. 909-918 : ill http://dx.doi.org/10.1016/j.micpro.2014.11.002

journal article

293

book article

Functional specification and testing of digital systemsUbar, Raimund-JohannesMultimicroprocessor systems: Proceedings of the 3rd Symposium, Stralsund, oct. 16-20, 1989, Vol 11989 / p. 207-217

book article

294

book article

Functional test generation for finite state machinesUbar, Raimund-Johannes; Brik, Marina; Jutman, Artur; Raik, Jaan; Bengtsson, Tomas; Kumar, ShashiBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 205-208 : ill

book article

295

book article

Functional test program generation for digital systemsUbar, Raimund-Johannes; Dušina, Julia; Krupnova, Helena; Storožev, Sergei; Zaugarov, ViktorTestmethoden und Zuverlässigkeit von Schaltungen und Systemen : proceedings of the 6th workshop, Vaals (Niederlande), March 6-8, 19941994 / p. 14-18: ill

book article

296

book article

Funktsionaalsete alternatiivsete graafide mudeli süntees digitaallülitusteleKivi, E.; Ubar, Raimund-JohannesXXXII üliõpilaste teaduslik-tehnilise konverentsi ettekannete teesid : pühendatud V. I. Lenini 110. sünniaastapäevale : 16.-18. aprill 19801981 / lk. 91 https://www.ester.ee/record=b1322611*est

book article

297

book article

GA-based test generation for sequential circuitsBrik, Marina; Raik, Jaan; Ubar, Raimund-Johannes; Ivask, EeroProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 30-34

book article

298

book article

Gate-level modelling of NBTI-induced delays under process variationsCopetti, Thiago; Cardoso Medeiros, Guilherme; Bolzani Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 75-80 : ill http://dx.doi.org/10.1109/LATW.2016.7483343

book article

299

book article

Generating directed tests for C programs using RTL ATPGRaik, Jaan; Drenkhan, Tiia; Jenihhin, Maksim; Viilukas, Taavi; Karputkin, Anton; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)2012 / p. 1-6

book article

300

book article

Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault modelUbar, Raimund-Johannes; Borrione, DominiqueXI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings1998 / p. 51-54 https://ieeexplore.ieee.org/document/715409

book article

Ubar, Raimund-Johannes (TTÜ author)

types of item

CV 63

author 57

name of the person 28

subject term 1