Searching - TalTech Research Portal

display

sort

26

book article

Biotundlikud süsteemid molekulaarselt jäljendatud elektrit juhtivatest polümeeridestÖpik, Andres; Reut, Jekaterina; Sõritski, Vitali; Tretjakov, AlekseiTallinna Tehnikaülikooli aastaraamat 20122013 / lk. 40-44 : ill

book article

27

book article

BIST analyzer : a training platform for SoC testing [Electronic resource]Jutman, Artur; Tšertov, Anton; Tšepurov, Anton; Aleksejev, Igor; Ubar, Raimund-Johannes; Wuttke, Heinz-Dietrich37th Annual Frontiers in Education Conference : Global Engineering : Knowledge Without Borders, Opportunities Without Passports : Milwaukee, Wisconsin, October 10-13, 20072007 / p. S3H-8-S3H-13 : ill. [CD-ROM] http://dx.doi.org/10.1109/FIE.2007.4418125

book article

28

book article

CAC 2.0 : a corrupt and correct logic locking technique resilient to structural analysis attacksAksoy, Levent; Yasin, Muhammad; Pagliarini, Samuel2024 IEEE 25th Latin American Test Symposium (LATS) : 9-12 April 2024 (2024)2024 https://doi.org/10.1109/LATS62223.2024.10534592 Article at Scopus

book article

29

book article

A CAD system for teaching digital testUbar, Raimund-Johannes; Ivask, Eero; Paomets, Priidu; Raik, JaanBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 369-372: ill

book article

30

journal article

Cal-Techist PocketronicuniToomsalu, ArvoA & A2005 / 4, lk. 9-12 https://artiklid.elnet.ee/record=b1018130*est

journal article

31

book article

Capacitance measurement with MSP430 microcontrollersMärtens, Olev; Pille, Siim; Reidla, MarkoEDERC2014 : proceedings of the 6th European Embedded Design in Education and Research Conference, 11-12 September 2014, Milan, Italy2014 / p. 260-263 : ill

book article

32

journal article EST / journal article ENG

Capacitance-to-digital: A single chip detector for capillary electrophoresisDrevinskas, Tomas; Kaljurand, Mihkel; Maruška, AudriusElectrophoresis2014 / p. 2401-2407 : ill https://doi.org/10.1002/elps.201300468 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

33

journal article

Chip-to-Chip authentication method based on SRAM PUF and public key cryptographyKarageorgos, Ioannis; Isgenc, Mehmet Meric; Pagliarini, Samuel Nascimento; Pileggi, LarryJournal of hardware and systems security2019 / p. 382–396 : ill https://doi.org/10.1007/s41635-019-00080-y

journal article

34

journal article

Circuit simulation program oriented physical modeling of integrated circuit elementsRang, Toomas; Tarnay, K.; Szekely, V.Periodica polytechnica. Electrical engineering = Электротехника1980 / p. 37-45 https://www.ester.ee/record=b1198855*est

journal article

35

book article

Code coverage analysis for concurrent programming languages using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesProceedings of the 12th European Workshop on Dependable Computing : EWDC 2009 : Toulouse, France, May 14-15, 20092009 / [4] p. : ill https://hal.archives-ouvertes.fr/hal-00381559

book article

36

book article

Combining symbolic techniques with topological approach in test generationUbar, Raimund-JohannesProceedings of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 19961996 / p. 377-382

book article

37

book article

A compact 16*16 CMOS cellular neural network chipPaasio, Ari; Dawidziuk, Adam; Porra, VeikkoBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 171-174: ill

book article

38

book article

Compact avalanche transistor model for circuit simulation of Bi and BiCMOS cellsBubennikov, Alexander N.; Kobosev, Gennady; Kozhuhov, D.; Uchenov, A.BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 21994 / p. 523-527: ill https://www.ester.ee/record=b2150914*est

book article

39

book article

Computational kernel extraction for synthesis of power-managed sequential componentsSudnitsõn, AleksanderProceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems : ICECS'2002, Dubrovnik, Croatia2002 / p. 749-752 https://ieeexplore.ieee.org/abstract/document/1046277

book article

40

journal article

Construction of the tests of combinational circuit failures by analyzing the orthogonal disjunctive normal forms represented by the alternative graphsMatrosova, A.Yu.; Pleshkov, A.G.; Ubar, Raimund-JohannesAutomation and remote control2005 / p. 313-327 : ill http://dx.doi.org/10.1007/s10513-005-0054-9

journal article

41

journal article

Decision diagrams - from a mathematical notion to engineering applicationsStankovic, Radomir S.; Ubar, Raimund-Johannes; Astola, JaakkoFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 281-301 : ill http://dx.doi.org/10.2298/FUEE1103281S

journal article

42

book article

Defect-oriented test- and layout-generation for standard-cell ASIC designsSudbrock, Joachim; Raik, Jaan; Ubar, Raimund-Johannes; Kuzmicz, Wieslaw; Pleskacz, Witold A.Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 79-82 : ill https://ieeexplore.ieee.org/document/1559781

book article

43

book article

Defect-oriented test generation using probabilistic estimationCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 131-136 : ill

book article

44

book article

DefSim - the defective ICPleskacz, Witold A.; Jutman, Artur; Ubar, Raimund-Johannes; Devadze, SergeiDATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 20072007 / p. s96 (2 p.)

book article

45

book article

DefSim: CMOS defects on chip for research and educationPleskacz, Witold A.; Borejko, Tomasz; Walkanis, A.; Stopjakova, Viera; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 74-79 : ill

book article

46

book article

DefSim: measurement environment for CMOS defectsBorejko, Tomasz; Jutman, Artur; Pleskacz, Witold A.; Ubar, Raimund-Johannes2006 25th International Conference on Microelectronics : Belgrade, Serbia and Montenegro, 14-17 May 2006 : proceedings. Volume 22006 / p. 679-682 https://ieeexplore.ieee.org/document/1651048

book article

47

book article

Delay testing of asynchronous NoC interconnectsBengtsson, Tomas; Jutman, Artur; Kumar, Shashi; Ubar, Raimund-JohannesProceedings of the 12th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2005 : Krakow, Poland, 22-25 June, 2005. Vol. 1 of 22005 / p. 419-424 : ill

book article

48

book article

Design and optimization of super-speed CMOS/CBiCMOS circuits based on TCAD and time-logical simulatorBubennikov, Alexander; Blinnik, Semen B.BEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 473-474: ill

book article

49

book

Design and test technology for dependable systems-on-chip2011 https://www.ester.ee/record=b4467408*est

book

50

book article

Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraintsAmin, Mohsin; Tagel, Mihkel; Jervan, Gert; Hollstein, Thomas7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip : July 9-11, 2012 : York, United Kingdom : proceedings2012 / [6 p.] : ill https://ieeexplore.ieee.org/document/6322901

book article

integraallülitused (subject term)

types of item

subject term 1