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76

book article

Faults and fault models for integrated circuits and systems [Electronic resource] : [slides]Ubar, Raimund-JohannesDesign and Test Technology for Dependable Hardware/Software Systems : DEDIS/DAAD Summer Academy : BTU Cottbus, Sept. 1st-12th, 20082008 / [64] p. : ill. [CD-ROM]

book article

77

book article

Finite state machines with datapath partitioning for low power synthesisSudnitsõn, AleksanderProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 163-168 : ill

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78

book article

Foreword to the 12th IEEE DDECS SymposiumPliva, Zdenek; Manhaeve, Hans; Renovell, Michel; Novak, Ondrej; Ubar, Raimund-Johannes; Drabkova, JindraProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 15-17, 2009, Liberec, Czech Republic2009 / p. iii http://dx.doi.org/10.1109/DDECS.2009.5012081

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79

journal article

From virtual characterization to test-chips : DFM analysis through pattern enumerationMartins, Mayler G.A.; Pagliarini, Samuel Nascimento; Isgenc, Mehmet Meric; Pileggi, LarryIEEE transactions on computer-aided design of integrated circuits and systems2020 / p. 520-532 https://doi.org//10.1109/TCAD.2018.2889772

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80

book article

Gate-level modelling of NBTI-induced delays under process variationsCopetti, Thiago; Cardoso Medeiros, Guilherme; Bolzani Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 75-80 : ill http://dx.doi.org/10.1109/LATW.2016.7483343

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81

dissertation

Hardware realization of lattice-based post-quantum cryptography = Võrel põhinev post-kvant-krüptograafia riistvaraline realisatsioonImran, Malik2023 https://www.ester.ee/record=b5571216*est https://doi.org/10.23658/taltech.33/2023 https://digikogu.taltech.ee/et/Item/75aeb070-cb8b-4511-beaf-cbea3fca147d https://www.ester.ee/record=b5571216*est

dissertation

Related publications 6

82

book

Hardware/software co-design for programmable systems-on-chipSklyarov, Valery; Skliarova, Iouliia; Silva, João; Rjabov, Artjom; Sudnitsõn, Aleksander; Cardoso, Cláudia2014 http://www.ester.ee/record=b3087107*est

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83

journal article

A healthier chip?Ubar, Raimund-Johannes; Fridolin, Ivo; Meigas, Kalju; Min, MartPublic service review : European Union2010 / p. 132-133 : ill

journal article

84

book article

High-level decision diagram based fault models for targeting FSMsRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi9th EUROMICRO Conference on Digital Systems Design : Architectures, Methods and Tools (DSD 2006) : 30 August 2006-1 September 2006, Cavtat near Dubrovnik, Croatia : proceedings2006 / p. 353-358 : ill http://dx.doi.org/10.1109/DSD.2006.60

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85

book article

High-Level Decision Diagram manipulations for code coverage analysisMinakova, Karina; Reinsalu, Uljana; Tšepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Ellervee, PeeterBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 207-210 : ill

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86

book article

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

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87

book article

High-level modeling and testing of multiple control faults in digital systemsJasnetski, Artjom; Oyeniran, Adeboye Stephen; Tšertov, Anton; Schölzel, Mario; Ubar, Raimund-JohannesFormal proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 20-22, 2016, Košice, Slovakia2016 / [6] p. : ill http://dx.doi.org/10.1109/DDECS.2016.7482445

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88

journal article EST / journal article ENG

High-speed SABER key encapsulation mechanism in 65nm CMOSImran, Malik; Almeida, Felipe; Basso, Andrea; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoJournal of cryptographic engineering2023 / p. 461-471 : ill https://doi.org/10.1007/s13389-023-00316-2 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

Related publications 1

Hardware realization of lattice-based post-quantum cryptography = Võrel põhinev post-kvant-krüptograafia riistvaraline realisatsioon

89

newspaper article

Hiina võis sanktsioonide kiuste jõuda uue kiibitehnoloogiani [Võrguväljaanne]Einama, KaidoPostimees2022 Hiina võis sanktsioonide kiuste jõuda uue kiibitehnoloogiani

newspaper article

90

book article

How to emulate Network-on-Chip?Ellervee, Peeter; Jervan, GertProceedings of the IEEE East-West Design & Test Workshop (EWDTW'06) : Sochi, Russia, September 15-19, 20062006 / p. 282-286 : ill

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91

book article

Hybrid BIST optimization using reseeding and test set compactionJervan, Gert; Orasson, Elmet; Kruus, Helena; Ubar, Raimund-Johannes10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings2007 / p. 596-603 : ill http://dx.doi.org/10.1109/DSD.2007.4341529

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92

journal article EST / journal article ENG

Hybrid protection of digital FIR filtersAksoy, Levent; Nguyen, Quang-Linh; Almeida, Felipe; Raik, Jaan; Flottes, Marie-Lise; Dupuis, Sophie; Pagliarini, Samuel NascimentoIEEE transactions on Very Large Scale Integration (VLSI) Systems2023 / p. 812-825 : ill https://doi.org/10.1109/TVLSI.2023.3253641 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

93

journal article

I²L új irányrat a bipoláris technikában IRang, ToomasMérés és automatika: megjelenik a Méréstechnikai és Automatizálási Tudományos Egyesület Szerkesztésében1979 / p. 191-195

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94

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I²L, új irányrat a bipoláris technikában IIRang, ToomasMérés és automatika: megjelenik a Méréstechnikai és Automatizálási Tudományos Egyesület Szerkesztésében1979 / p. 279-283

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95

journal article

IEEE Norchip 2003. a. konverentsEllervee, PeeterA & A2004 / 1, lk. 48-49 https://artiklid.elnet.ee/record=b1015000*est

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96

journal article

Impact of orientation on the bias of SRAM-based PUFsAbideen, Zain Ul; Wang, Rui; Perez, Tiago Diadami; Schrijen, Geert-Jan; Pagliarini, Samuel NascimentoarXiv.org2023 / 7 p. : ill https://doi.org/10.48550/arXiv.2308.06730

journal article

Related publications 1

Leveraging FPGA Reconfigurability as an Obfuscation Asset = FPGA ümberkonfigureeritavuse rakendamine hägustamise vahendina

97

journal article

Impact of orientation on the bias of SRAM-based PUFsAbideen, Zain Ul; Wang, Rui; Perez, Tiago Diadami; Schrijen, Geert-Jan; Pagliarini, Samuel NascimentoIEEE design & test2024 / p. 14-20 https://doi.org/10.1109/MDAT.2023.3322621

journal article

Related publications 1

Leveraging FPGA Reconfigurability as an Obfuscation Asset = FPGA ümberkonfigureeritavuse rakendamine hägustamise vahendina

98

book article

Improving the efficiency of timing simulation in digital circuits by using structurally synthesized BDDsUbar, Raimund-Johannes; Jutman, Artur; Peng, Z.IEEE Norchip Conference2000 / p. 254-261

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99

book

Informal Digest of Papers : 10 IEEE European Test Symposium : Tallinn, Estonia, May 22-25, 20052005 https://www.ester.ee/record=b2055139*est

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100

journal article

Integraallülituste hindToomsalu, ArvoA & A2007 / 3, lk. 20-32 : ill

journal article

integraallülitused (subject term)

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