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Defect-oriented fault simulation and test generation in digital circuits (title)
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book article
Defect-oriented fault simulation and test generation in digital circuits
Kuzmicz, W.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California
2001
/
p. 365-371
https://ieeexplore.ieee.org/document/915257
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keyword
32
1.
test generation and fault diagnosis
2.
Multi-valued Simulation for Hazard Detection in Digital Circuits
3.
Fault Injection Simulation
4.
fault simulation
5.
fault simulation with critical path tracing
6.
high-level fault simulation
7.
Parallel Fault Simulation with Critical Path Backtracing
8.
parallel fault-simulation
9.
digital circuits
10.
digital circuits and systems
11.
Structural Decision Diagrams for Modeling Digital Circuits
12.
adaptive test strategy generation
13.
automated test pattern generation
14.
automatic test case generation
15.
automatic test pattern generation
16.
automatic test program generation
17.
behaviour level test generation
18.
functional test generation
19.
Hierarchical Multi-level Test Generation
20.
high-level test data generation
21.
highlevel test generation
22.
implementation-independent test generation
23.
offline test generation
24.
provably correct test generation
25.
test generation
26.
Test Group Generation for Detecting Multiple Faults
27.
test program generation
28.
digital real time simulation
29.
digital shipping simulation
30.
similar material simulation test
31.
digital test
32.
Digital test and testable design
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