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301

artikkel kogumikus

Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault modelUbar, Raimund-Johannes; Borrione, DominiqueXI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings1998 / p. 51-54

artikkel kogumikus

302

artikkel kogumikus

Generic interconnect BIST for Network-on-ChipJutman, Artur; Ubar, Raimund-Johannes; Raik, JaanDDECS : 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : April 13-16, 2005, Sopron, Hungary : proceedings2005 / p. 224-227 : ill

artikkel kogumikus

303

artikkel kogumikus

A generic synthesizable NoC switch with a scalable testbenchGovind, Vineeth; Raik, Jaan; Ubar, Raimund-JohannesBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 91-94 : ill

artikkel kogumikus

304

artikkel ajakirjas

Guest editorialLande, Tor Sverre; Ubar, Raimund-JohannesAnalog integrated circuits and signal processing1999 / 1, p. 5-6

artikkel ajakirjas

305

artikkel ajakirjas

[H. Bleeker, P.Van Den Eijnden, F.De Jong. Boundary-scan test. Boston : Kluwer Academic, 1993. 225 p. : book review]Ubar, Raimund-JohannesEngineering applications of artificial intelligence1994 / p. 86-87 https://www.ester.ee/record=b1200126*est

artikkel ajakirjas

306

raamat

Handbook of testing electronic systemsNovak, Ondrej; Gramatova, Elena; Ubar, Raimund-Johannes; Jutman, Artur; Raik, Jaan2005 https://www.ester.ee/record=b2102523*est

raamat

307

artikkel ajalehes

Hea teaduse odav väljamüükUbar, Raimund-JohannesPostimees2017 / lk. 6 https://teadus.postimees.ee/4343295/raimund-ubar-hea-teaduse-odav-valjamuuk

artikkel ajalehes

308

artikkel ajakirjas

A healthier chip?Ubar, Raimund-Johannes; Fridolin, Ivo; Meigas, Kalju; Min, MartPublic service review : European Union2010 / p. 132-133 : ill

artikkel ajakirjas

309

artikkel kogumikus

Hierarchical analysis of short defects between metal lines in CMOS ICPleskacz, Witold A.; Jenihhin, Maksim; Raik, Jaan; Rakowski, Michal; Ubar, Raimund-Johannes; Kuzmicz, WieslawProceedings : 11th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools : (DSD 2008) : September 3-5, 2008, Parma, Italy2008 / p. 729-734 : ill https://ieeexplore.ieee.org/document/4669309

artikkel kogumikus

310

artikkel kogumikus

Hierarchical approach to test generation for digital systems at system, circuit and defect levelsUbar, Raimund-Johannes45. Internationales Wissenschaftliches Kolloquium, 04.-06.10.2000 : Tagungsband2000 / S. 711-716 : Ill

artikkel kogumikus

311

artikkel ajakirjas

Hierarchical approaches to test generation and fault simulationUbar, Raimund-JohannesRadioelectronics and informatics2003 / p. 204

artikkel ajakirjas

312

artikkel kogumikus

A hierarchical automatic test pattern generator based on using alternative graphsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 4th International Workshop Mixed Design of Integrated Circuits and Systems : MIXDES'97 : Poznan, Poland, 12-14 June 19971997 / p. 415-420

artikkel kogumikus

313

artikkel kogumikus

Hierarchical calculation of malicious faults for evaluating the fault-toleranceUbar, Raimund-Johannes; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, PeeterProceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China2008 / p. 222-227 : ill https://ieeexplore.ieee.org/document/4459544

artikkel kogumikus

314

artikkel kogumikus

Hierarchical concurrent test generation for synchronous sequential circuitsUbar, Raimund-Johannes; Brik, MarinaProceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2000 : Gdynia, Poland, 15-17 June 20002000 / p. 533-538 : ill

artikkel kogumikus

315

artikkel kogumikus

Hierarchical defect level test quality analysisBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum2000 / [11] p

artikkel kogumikus

316

artikkel kogumikus

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop2000 / p. 151-156 https://ieeexplore.ieee.org/document/873781

artikkel kogumikus

317

artikkel kogumikus

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings2000 / p. 69-74 : ill

artikkel kogumikus

318

artikkel kogumikus

Hierarchical design error diagnosis in combinational circuits by stuck-at fault test patternsUbar, Raimund-Johannes; Jutman, ArturProceedings of the 6th International Conference on Mixed Design of Integrated Circuits and Systems : MIXDES'99 : Krakow, Poland, 17-19 June 19991999 / p. 437-442 : ill

artikkel kogumikus

319

artikkel kogumikus

Hierarchical fault diagnosis in embedded digital systems with multi-level decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Evartson, Teet; Lensen, Harri; Aarna, Margit5th International Conference on Industrial Automation = Cinquieme Conference Internationale sur l'Automatisation Industrielle : June 11-13, 2007, Montreal, Canada2007 / [6] p. [CD-ROM]

artikkel kogumikus

320

artikkel kogumikus

Hierarchical fault simulation for finite state machinesBrik, Marina; Raik, Jaan; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 145-148 : ill

artikkel kogumikus

321

artikkel kogumikus

Hierarchical fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaInternational Symposium on Signals, Circuits and Systems : SCS 2001 : July 10-11, 2001, Iasi, Romania : proceedings2001 / p. 181-184 : ill

artikkel kogumikus

322

artikkel kogumikus

Hierarchical identification of NBTI-critical gates in nanoscale logicKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, MaksimLATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 20142014 / [6] p. : ill

artikkel kogumikus

323

artikkel kogumikus

Hierarchical identification of untestable faults in sequential circuitsRaik, Jaan; Ubar, Raimund-Johannes; Krivenko, Anna; Kruus, Margus10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings2007 / p. 668-671 : ill http://dx.doi.org/10.1109/DSD.2007.4341539

artikkel kogumikus

324

artikkel ajakirjas

Hierarchical physical defect reasoning in digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Brik, MarinaEstonian journal of engineering2011 / 3, p. 185-200

artikkel ajakirjas

325

artikkel kogumikus

Hierarchical test generation based on alternative graph modelUbar, Raimund-JohannesProceedings of the Second Workshop on Hierarchical Test Generation : Microelectronics Technology Park, Duisburg, Germany, September 25-26, 19951995 / p. 18

artikkel kogumikus

Ubar, Raimund-Johannes (autor)

teaviku laadid

CV 61

autor 57

tema kohta 28

märksõna 1