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journal article

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

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77

journal article

Holistic IJTAG-based external and internal fault monitoring in UAVsAhmed, Foisal; Jenihhin, MaksimarXiv.org2023 / 6 p. : ill https://doi.org/10.48550/arXiv.2303.01816

journal article

78

book article

Hybrid BIST optimization for core-based systems with test pattern broadcastingUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, ZeboDELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : 28-30 January 2004, Perth, Australia : proceedings2004 / p. 3-8 : ill https://ieeexplore.ieee.org/document/1409808

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79

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Hybrid BIST time minimization for core-based systems with STUMPS architectureJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings2003 / p. 225-232 : ill https://ieeexplore.ieee.org/document/1250116

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80

journal article EST / journal article ENG

Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuitsJenihhin, Maksim; Squillero, Giovanni; Tihhomirov, Valentin; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2016 / p. 273-289 : ill https://doi.org/10.1007/s10836-016-5589-x Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

81

book article

Identification and rejuvenation of NBTI-critical paths in nanoscale logic circuitsJenihhin, Maksim1st International Workshop on Reliability and Aging in Forthcoming Electronic Systems : May 28-29, 2015, Cluj-Napoca, Romania2015 / [1] p

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82

book article

Identifying NBTI-critical paths in nanoscale logicUbar, Raimund-Johannes; Vargas, Fabian; Jenihhin, Maksim; Raik, Jaan; Kostin, Sergei; Bolzani Poehls, Leticia16th Euromicro Conference series on Digital System Design : DSD 2013 : proceedings : 4-6 September 2013, Santander, Spain2013 / p. 136-141 : ill

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83

journal article

Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill

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84

book article

Implementation-independent functional test for transition delay faults in microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia2020 / p. 646-650 https://doi.org/10.1109/DSD51259.2020.00105

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85

book article

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

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86

book article

Implementation-independent test generation for a large class of faults in RISC processor modulesJenihhin, Maksim; Oyeniran, Adeboye Stephen; Raik, Jaan; Ubar, Raimund-Johannes24th Euromicro Conference on Digital System Design (DSD)2021 https://doi.org/10.1109/DSD53832.2021.00090

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87

book article

An iterative approach to test time minimization for parallel hybrid BIST architectureUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, Z.5th IEEE Latin-American Test Workshop - LATW 2004 : Cartagena, Colombia, 2004 : digest of papers2004 / p. 98-103 : ill

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88

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An iterative approach to test time minimization for parallel hybrid BIST architecturesUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, Z.System-on-Chip Conference 2004 : Bastad, Sweden2004 / p. ?

book article

89

book article

JÄNES : a NAS framework for ML-based EDA applicationsSelg, Hardi; Jenihhin, Maksim; Ellervee, PeeterIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems2021 https://doi.org/10.1109/DFT52944.2021.9568321

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90

book article

Layout to logic defect analysis for hierarchical test generationJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Pleskacz, Witold A.; Rakowski, MichalProceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland2007 / p. 35-40 : ill http://dx.doi.org/10.1109/DDECS.2007.4295251

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91

book article

Localization of bugs in processor designs using zamiaCAD frameworkTšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions : Austin, USA, December 10–12, 20122012 / p. 1-6 https://ieeexplore.ieee.org/document/6519733

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92

book article

Measuring and identifying aging-critical paths in FPGAsPfeifer, Petr; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Pliva, ZdenekMEDIAN 2015 : the 4th Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : March 13, 2015, Grenoble, France2015 / p. 56-61 : ill

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93

book article

A methodology for automated mining of compact and accurate assertion setsHeidari Iman, Mohammad Reza; Raik, Jaan; Jenihhin, Maksim; Jervan, Gert; Ghasempouri, Tara2021 IEEE Nordic Circuits and Systems Conference (NorCAS) : Oslo, Norway, October 26-272021 / 7 p. : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9599865 https://doi.org/10.1109/NorCAS53631.2021.9599865

book article

94

dissertation

Methods to optimize functional safety assessment for automotive integrated circuits = Meetodid autotööstuse kiipide funktsionaalse ohutuse hindamise optimeerimiseksBagbaba, Ahmet Cagri2022 https://doi.org/10.23658/taltech.9/2022 https://digikogu.taltech.ee/et/Item/58b0b89d-b1ba-4a73-ba53-850910d697b5 https://www.ester.ee/record=b5491885*est

dissertation

Seotud publikatsioonid 10

95

journal article

Mixed hierarchical-functional fault models for targeting sequential coresRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi; Jenihhin, MaksimJournal of systems architecture2008 / 3/4, p. 465-477 : ill https://www.sciencedirect.com/science/article/abs/pii/S1383762107001166

journal article

96

book article

Mixed-level identification of fault redundancy in microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Gürsoy, Cemil Cem; Raik, JaanLATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 20192019 / 6 p. : ill https://doi.org/10.1109/LATW.2019.8704591

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97

book article

MLC: a machine learning based checker for soft error detection in embedded processorsNosrati, Nooshin; Jenihhin, Maksim; Navabi, ZainalabedinProceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 20222022 / Code 183305 https://doi.org/10.1109/IOLTS56730.2022.9897309 Article at Scopus Article at WOS

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98

book article

Modeling for multi-view interference analysis of design aspects in MPSoC designsVain, Jüri; Apneet Kaur; Tsiopoulos, Leonidas; Raik, Jaan; Jenihhin, MaksimRESCUE 2017 : Workshop on Reliability, Security and Quality : ETS17 Fringe Workshop, May 25-26, 2017, Limassol, Cyprus2017 / p. 1-6 http://www.ets17.org.cy/workshop/rescue-workshop.html

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99

book article

Modeling gate-level abstraction hierarchy using graph convolutional neural networks to predict functional de-rating factorsBalakrishnan, Aneesh; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Jenihhin, Maksim2019 NASA/ESA conference on adaptive hardware and systems AHS 2019 : proceedings2019 / p. 72-78 : ill https://doi.org/10.1109/AHS.2019.00007

book article

Seotud publikatsioonid 1

A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseks

100

book article

Modeling microprocessor faults on high-level decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Istenberg, Martin; Wuttke, Heinz-DietrichDSN 2008 : supplemental : 2008 IEEE International Conference on Dependable Systems & Networks With FTCS & DCC (DSN) : June 24-27, 2008, Anchorage, Alaska2008 / p. C17-C22 : ill. [CD-ROM] https://webhost.laas.fr/TSF/WDSN08/2ndWDSN08(LAAS)_files/Slides/WDSN08S-04-Ubar.pdf

book article

Jenihhin, Maksim (TTÜ author)

types of item

author 14

CV 9

name of the person 7