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Pleskacz, Witold A. (author)
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1
book article
CMOS defects analysis using DefSim measurement environment
Pleskacz, Witold A.
;
Borejko, Tomasz
;
Walkanis, A.
;
Stopjakova, Viera
;
Jutman, Artur
;
Ubar, Raimund-Johannes
Informal Digest of Papers : Eleventh IEEE European Test Symposium : ETS 2006 : 21-24 May 2006, Southampton, United Kingdom
2006
/
p. 241-246 : ill
book article
2
book article
Defect oriented fault coverage of 100stuck-at fault test sets
Blyzniuk, M.
;
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Lobur, M.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Proceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2000 : Gdynia, Poland, 15-17 June 2000
2000
/
p. 511-516 : ill
book article
3
book article
Defect-oriented fault simulation and test generation in digital circuits
Kuzmicz, W.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California
2001
/
p. 365-371
https://ieeexplore.ieee.org/document/915257
book article
4
book article
Defect-oriented library builder and hierarchical test generation
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001 : Fourth International Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems : Györ, Hungary, April 18-20, 2001
2001
/
p. 163-168 : ill
book article
5
book article
Defect-oriented test- and layout-generation for standard-cell ASIC designs
Sudbrock, Joachim
;
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Kuzmicz, Wieslaw
;
Pleskacz, Witold A.
Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 2005
2005
/
p. 79-82 : ill
https://ieeexplore.ieee.org/document/1559781
book article
6
book article
Defect-oriented test generation and fault simulation in the environment of MOSCITO
Schneider, Andre
;
Diener, Karl-Heinz
;
Gramatova, Elena
;
Fisherova, Maria
;
Ivask, Eero
;
Ubar, Raimund-Johannes
;
Pleskacz, Witold A.
;
Kuzmicz, W.
BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia
2002
/
p. 303-306 : ill
book article
7
book article
Defect-oriented test generation using probabilistic estimation
Cibakova, Tatiana
;
Fischerova, Maria
;
Gramatova, Elena
;
Kuzmicz, W.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Proceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 2000
2001
/
p. 131-136 : ill
book article
8
book article
Defects, faults and fault models
Gramatova, Elena
;
Fisherova, Maria
;
Ubar, Raimund-Johannes
;
Pleskacz, Witold A.
Handbook of testing electronic systems
2005
/
p. 26-96 : ill
book article
9
book article
DefSim - the defective IC
Pleskacz, Witold A.
;
Jutman, Artur
;
Ubar, Raimund-Johannes
;
Devadze, Sergei
DATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 2007
2007
/
p. s96 (2 p.)
book article
10
journal article
DefSim: a remote laboratory for studying physical defects in CMOS digital circuits
Pleskacz, Witold A.
;
Stopjakova, Viera
;
Borejko, Tomasz
;
Jutman, Artur
;
Walkanis, Andrzej
IEEE transactions on industrial electronics
2008
/
6, p. 2405-2415 : ill
https://www.researchgate.net/publication/3219964_DefSim_A_Remote_Laboratory_for_Studying_Physical_Defects_in_CMOS_Digital_Circuits
journal article
11
book article
DefSim: CMOS defects on chip for research and education
Pleskacz, Witold A.
;
Borejko, Tomasz
;
Walkanis, A.
;
Stopjakova, Viera
;
Jutman, Artur
;
Ubar, Raimund-Johannes
7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings
2006
/
p. 74-79 : ill
book article
12
book article
DefSim: measurement environment for CMOS defects
Borejko, Tomasz
;
Jutman, Artur
;
Pleskacz, Witold A.
;
Ubar, Raimund-Johannes
2006 25th International Conference on Microelectronics : Belgrade, Serbia and Montenegro, 14-17 May 2006 : proceedings. Volume 2
2006
/
p. 679-682
https://ieeexplore.ieee.org/document/1651048
book article
13
book article
DefSim-based exercises for studying defects in CMOS gates
Jutman, Artur
;
Pleskacz, Witold A.
;
Boiko, Nikolai
;
Ubar, Raimund-Johannes
EWME 2006 proceedings : 6th International Workshop on Microelectronics Education : 8-9 June, 2006, Stockholm, Sweden
2006
/
p. 23-26 : ill
book article
14
book article
Deterministic defect-oriented test generation for combinational circuits
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Sudbrock, Joachim
;
Kuzmicz, Wieslaw
;
Pleskacz, Witold A.
LATW 2005 : 6th IEEE Latin-American Test Workshop : March 30 - April 2, 2005, Salvador, Bahia, Brazil : [digest of papers]
2005
/
p. 325-330 : ill
book article
15
book article
DOT: new deterministic defect-oriented ATPG tool
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Sudbrock, Joachim
;
Kuzmicz, Wieslaw
;
Pleskacz, Witold A.
European Test Symposium : ETS 2005 : 22-25 May 2005, Tallinn, Estonia : proceedings
2005
/
p. 96-101 : ill
book article
16
book article
Hierarchical analysis of short defects between metal lines in CMOS IC
Pleskacz, Witold A.
;
Jenihhin, Maksim
;
Raik, Jaan
;
Rakowski, Michal
;
Ubar, Raimund-Johannes
;
Kuzmicz, Wieslaw
Proceedings : 11th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools : (DSD 2008) : September 3-5, 2008, Parma, Italy
2008
/
p. 729-734 : ill
https://ieeexplore.ieee.org/document/4669309
book article
17
book article
Hierarchical defect level test quality analysis
Blyzniuk, M.
;
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Lobur, M.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
VILAB User Forum
2000
/
[11] p
book article
18
book article
Hierarchical defect-oriented fault simulation for digital circuits
Blyzniuk, M.
;
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Lobur, M.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings
2000
/
p. 69-74 : ill
book article
19
book article
Hierarchical defect-oriented fault simulation for digital circuits
Blyzniuk, M.
;
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Lobur, M.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE European Test Workshop
2000
/
p. 151-156
https://ieeexplore.ieee.org/document/873781
book article
20
journal article
Hierarchical test generation for combinational circuits with real defects coverage
Cibakova, Tatiana
;
Fischerova, Maria
;
Gramatova, Elena
;
Kuzmicz, W.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Microelectronics reliability
2002
/
p. 1141-1149 : ill
https://www.sciencedirect.com/science/article/pii/S002627140200080X
journal article
21
book article
Layout to logic defect analysis for hierarchical test generation
Jenihhin, Maksim
;
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Pleskacz, Witold A.
;
Rakowski, Michal
Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland
2007
/
p. 35-40 : ill
http://dx.doi.org/10.1109/DDECS.2007.4295251
book article
22
journal article
Module level defect simulation in digital circuits
Kuzmicz, Wieslaw
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Proceedings of the Estonian Academy of Sciences. Engineering
2001
/
4, p. 253-268
journal article
23
journal article
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement
Blyzniuk, M.
;
Kazymyra, I.
;
Kuzmicz, W.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
Microelectronics reliability
2001
/
p. 2023-2040 : ill
https://www.sciencedirect.com/science/article/pii/S0026271401000920
journal article
Number of records 23, displaying
1 - 23
author
5
1.
Pleskacz, Witold A.
2.
Mikulowski, Witold
3.
Piekoszewski, Witold
4.
Postek, Witold
5.
Respondek, Witold
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