Otsing - TalTech teadusportaal

Publikatsioonid
Profiilid
Uurimisrühmad
Registrid
Abi ja info
Switch to English

Publikatsioonid

Publikatsioonid

Otsing

Valitud kirjed 0

gate-level analysis (võtmesõna)

—

—

—

—

Lisa tingimus Liitotsing filter

Tühista

teaviku laadid

raamat ..

artikkel ajakirjas ..

artikkel ajalehes ..

artikkel kogumikus ..

dissertatsioon ..

Open Access ..

Teaduspublikatsioon ..

aasta

Toon andmeid..

Toon andmeid..

TTÜ struktuuriüksus

Toon andmeid..

Toon andmeid..

Toon andmeid..

Toon andmeid..

Toon andmeid..

Tühista

Kirjeid leitud 3
Vaata veel.. (1/137)
Ekspordi

ekspordi kõik päringu tulemused (3)
Salvesta TXT fail

Salvesta PDF fail

prindi
Märgitud kirjetega toimetamiseks ava valitud kirjed

kuva

reasta
1

artikkel kogumikus

A scalable technique to identify true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, JaanProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 152-157 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

artikkel kogumikus
2

artikkel ajakirjas EST / artikkel ajakirjas ENG

Fast identification of true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Jürimägi, LembitMicroelectronics reliability2018 / p. 252-261 : ill https://doi.org/10.1016/j.microrel.2017.11.027 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

artikkel ajakirjas EST / artikkel ajakirjas ENG
3

artikkel kogumikus

Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176

artikkel kogumikus

Kirjeid leitud 3, kuvan 1 - 3

1. gate-level analysis
2. gate-level circuit abstraction
3. gate-level netlist
4. register transfer and gate level simulation
5. hierarchical two-level analysis
6. system-level analysis
7. logic level and high level BDDs
8. Field Programmable Gate Array (FPGA)
9. field programmable gate arrays
10. field-programmable gate array
11. Field-Programmable Gate Array (FPGA)
12. field-programmable gate arrays
13. FPGA (field-programmable gate array)
14. GaTe
15. gate and register transfer levels
16. gate delay
17. gate driver
18. Gate Injection Transistor (GIT)
19. Golden gate assembly
20. insulated gate bipolar transistors
21. insulated gate-commutated thyristors
22. NBTI-critical gate
23. Opal Kelly ﬁeld programmable gate array (FPGA)
24. absolute sea level
25. airport level of service
26. arousal level
27. assurance level
28. behaviour level test generation
29. bi-level optimization
30. CO2 level in classrooms
31. CO2 level in classrooms and kindergartens
32. confidence level
33. country-level logistics
34. customer compatibility level
35. deep level
36. deep level traps
37. determination of the CO2 level
38. digitalisation level
39. distribution-level phasor measurement units (D-PMUs)
40. exposure level
41. extreme penetration level of non synchronous generation
42. extreme water level
43. graduate level
44. high level DD (HLDD)
45. high level synthesis
46. high-level control fault model
47. high-level control faults
48. high-level decision diagram
49. high-level decision diagrams
50. high-level decision diagrams (HLDD) synthesis
51. high-level expert group on AI
52. high-level fault coverage
53. high-level fault model
54. high-level fault simulation
55. high-level functional fault model
56. High-Level Synthesis (HLS)
57. high-level synthesis for test
58. high-level test data generation
59. improvement of safety level at enterprises
60. improvement of safety level at SMEs
61. level control
62. level set
63. level(s) methodology
64. level-crossing ADC
65. level-crossing analog-to-digital converters
66. level-crossing analogue-to-digital converters (ADC)
67. logic level
68. lower trophic level models
69. low-level control system transportation
70. low-level fault redundancy
71. low-level radiation
72. Low-level RF EMF
73. macro-level industry influences
74. mean sea level
75. module level power electronics (MLPE)
76. module-level power electronics (MLPE)
77. multi-level governance
78. multi-level inverter
79. multi-level modeling
80. multi-level perspective
81. multi-level perspective of sustainability transitions
82. multi-level selection and processing environment
83. operational level (OL)
84. Price level
85. Process/Product Sigma Performance Level (PSPL)
86. PV module level power electronics
87. Register Transfer Level - RTL
88. register transfer level modeling decision diagams
89. register-transfer level
90. relative sea level
91. relative sea-level change
92. RH level
93. school-level policies
94. sea level
95. sea level rise
96. sea level series
97. sea level trend
98. sea level: variations and mean
99. sea-level
100. sea-level changes
101. sea-level equation
102. Sea-level indicator
103. sea-level prediction
104. sea-level rise
105. sea-level trend
106. seven-level multilevel
107. skin conductance level
108. software level TMR
109. steel-level bureaucracy
110. strategic level decision makers
111. system level hazards
112. system level test
113. system planning level
114. system-level evaluation
115. task-level uninterrupted presence
116. three-level
117. three-level inverter
118. three-level neutral-point-clamped inverter
119. three-level NPC inverter
120. three-level T-type
121. three-level T-type inverter
122. three-level T-type quasi-impedance-source inverter (3L-T-type qZSI)
123. three-level voltage inverter
124. Tool Confidence Level
125. top-level domain
126. transaction-level modeling
127. treatment level
128. two-level inverter
129. undergraduate level
130. water level
131. water level fluctuation
132. water level measurements
133. water level reconstruction
134. water-level changes
135. voltage level
136. voltage level optimisation
137. 3-level T-type inverter

vaste

reasta

Otsing
Valikud 0

ilmumisaasta

autor

TTÜ struktuuriüksus

märksõna

seeria-sari

tema kohta

võtmesõna

TalTech Raamatukogu

Akadeemia tee 1

13519

TalTech koduleht TalTech Raamatukogu koduleht Digikogu Digiteek Teadusandmed

6203551

data@taltech.ee

TalTech Raamatukogu