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Jenihhin, Maksim 1981
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51
book article
Estonia : e-Design and EDA
Jenihhin, Maksim
50th DAC Global Forum
2013
/
[2] p
book article
52
book article
Extensible open-source framework for translating RTL VHDL IP cores to SystemC
Saif Abrar, Syed
;
Jenihhin, Maksim
;
Raik, Jaan
Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic
2013
/
p. 112-115
book article
53
journal article EST
/
journal article ENG
Fast and fair computation offloading management in a swarm of drones using a rating-based federated learning approach
Rahbari, Dadmehr
;
Alam, Muhammad Mahtab
;
Le Moullec, Yannick
;
Jenihhin, Maksim
IEEE Access
2021
/
p. 113832-113849
https://doi.org/10.1109/ACCESS.2021.3104117
Journal metrics at Scopus
Article at Scopus
Journal metrics at WOS
Article at WOS
journal article EST
/
journal article ENG
54
journal article EST
/
journal article ENG
Fast identification of true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Jürimägi, Lembit
Microelectronics reliability
2018
/
p. 252-261 : ill
https://doi.org/10.1016/j.microrel.2017.11.027
Journal metrics at Scopus
Article at Scopus
Journal metrics at WOS
Article at WOS
journal article EST
/
journal article ENG
55
book article
FP7 DIAMOND : design error diagnosis and correction success stories
Raik, Jaan
;
Jenihhin, Maksim
;
Könighofer, Robert
European Test Symposium (ETS), 2013, Avignon, France
2013
/
p. 1-6
book article
56
book article
FPGA-based implementation of EEG analyzer
Gorev, Maksim
;
Pesonen, Vadim
;
Mihhailov, Dmitri
;
Jenihhin, Maksim
;
Ellervee, Peeter
DATE'11 Friday Workshop on "Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing" : Grenoble, France, March 2011
2011
/
[1] p
book article
57
book article
FSMD RTL design manipulation for clock interface abstraction
Abrar, Syed Saif
;
Jenihhin, Maksim
;
Raik, Jaan
2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 10-13 August 2015, Kerala, India
2015
/
p. 463-468 : ill
http://dx.doi.org/10.1109/ICACCI.2015.7275652
book article
58
book article
Gate-level graph representation learning : a step towards the improved stuck-at faults analysis
Balakrishnan, Aneesh
;
Alexandrescu, Dan
;
Jenihhin, Maksim
;
Lange, Thomas
;
Glorieux, Maximilien
Proceedings of the Twenty Second International Symposium on Quality Electronic Design (ISQED) : Santa Clara, USA, 7-9 April 2021
2021
/
p. 24-30
https://doi.org/10.1109/ISQED51717.2021.9424256
book article
Seotud publikatsioonid
1
A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseks
59
book article
Gate-level modelling of NBTI-induced delays under process variations
Copetti, Thiago
;
Cardoso Medeiros, Guilherme
;
Bolzani Poehls, Leticia
;
Vargas, Fabian
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Ubar, Raimund-Johannes
LATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 2016
2016
/
p. 75-80 : ill
http://dx.doi.org/10.1109/LATW.2016.7483343
book article
60
book article
Generating directed tests for C programs using RTL ATPG
Raik, Jaan
;
Drenkhan, Tiia
;
Jenihhin, Maksim
;
Viilukas, Taavi
;
Karputkin, Anton
;
Tšepurov, Anton
;
Ubar, Raimund-Johannes
Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
2012
/
p. 1-6
book article
61
book article
Hierarchical analysis of short defects between metal lines in CMOS IC
Pleskacz, Witold A.
;
Jenihhin, Maksim
;
Raik, Jaan
;
Rakowski, Michal
;
Ubar, Raimund-Johannes
;
Kuzmicz, Wieslaw
Proceedings : 11th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools : (DSD 2008) : September 3-5, 2008, Parma, Italy
2008
/
p. 729-734 : ill
book article
62
book article
Hierarchical calculation of malicious faults for evaluating the fault-tolerance
Ubar, Raimund-Johannes
;
Devadze, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Jervan, Gert
;
Ellervee, Peeter
Proceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China
2008
/
p. 222-227 : ill
book article
63
book article
Hierarchical identification of NBTI-critical gates in nanoscale logic
Kostin, Sergei
;
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
LATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 2014
2014
/
[6] p. : ill
book article
64
book article
Hierarchical timing-critical paths analysis in sequential circuits
Jürimägi, Lembit
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
;
Devadze, Sergei
;
Kostin, Sergei
2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain
2018
/
6 p. : ill
https://doi.org/10.1109/PATMOS.2018.8464176
book article
65
book article
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors
Oyeniran, Adeboye Stephen
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings
2019
/
6 p. : ill
https://doi.org/10.1109/ETS.2019.8791526
book article
66
book article
High-level combined deterministic and pseudo-exhuastive test generation for RISC processors
Oyeniran, Adeboye Stephen
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Gürsoy, Cemil Cem
;
Raik, Jaan
2019 IEEE European Test Symposium (ETS) : proceedings
2019
/
6 p. : ill
https://doi.org/10.1109/ETS.2019.8791526
book article
67
book article
High-Level Decision Diagram manipulations for code coverage analysis
Minakova, Karina
;
Reinsalu, Uljana
;
Tšepurov, Anton
;
Raik, Jaan
;
Jenihhin, Maksim
;
Ubar, Raimund-Johannes
;
Ellervee, Peeter
BEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia
2008
/
p. 207-210 : ill
book article
68
book article
High-level decision diagram simulation for diagnosis and soft-error analysis
Raik, Jaan
;
Repinski, Urmas
;
Jenihhin, Maksim
;
Chepurov, Anton
Design and test technology for dependable systems-on-chip
2011
/
p. 294-309 : ill
book article
69
book article
High-level decision diagrams based coverage metrics for verification and test
Jenihhin, Maksim
;
Raik, Jaan
;
Tšepurov, Anton
;
Reinsalu, Uljana
;
Ubar, Raimund-Johannes
LATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 2009
2009
/
[6] p. : ill
http://dx.doi.org/10.1109/LATW.2009.4813792
book article
70
book article
High-level design error diagnosis using backtrace on decision diagrams
Raik, Jaan
;
Repinski, Urmas
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Tšepurov, Anton
28th Norchip Conference : Tampere, Finland, 15-16 November 2010 : conference program and papers
2010
/
[4] p. : ill
http://dx.doi.org/10.1109/NORCHIP.2010.5669486
book article
71
book article
High-level fault diagnosis in RISC processors with Implementation-Independent Functional Test
Oyeniran, Adeboye Stephen
;
Jenihhin, Maksim
;
Raik, Jaan
;
Ubar, Raimund-Johannes
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Nicosia, Cyprus : 04-06 July 2022
2022
/
p. 32-37
https://doi.org/10.1109/ISVLSI54635.2022.00019
book article
72
journal article
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors
Oyeniran, Adeboye Stephen
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
Journal of electronic testing : theory and applications
2020
/
p. 87-103
https://doi.org/10.1007/s10836-020-05856-7
journal article
73
journal article
Holistic IJTAG-based external and internal fault monitoring in UAVs
Ahmed, Foisal
;
Jenihhin, Maksim
arXiv.org
2023
/
6 p. : ill
https://doi.org/10.48550/arXiv.2303.01816
journal article
74
book article
Hybrid BIST optimization for core-based systems with test pattern broadcasting
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Jervan, Gert
;
Peng, Zebo
DELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : 28-30 January 2004, Perth, Australia : proceedings
2004
/
p. 3-8 : ill
http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10057
book article
75
book article
Hybrid BIST time minimization for core-based systems with STUMPS architecture
Jervan, Gert
;
Eles, Petru
;
Peng, Zebo
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings
2003
/
p. 225-232 : ill
book article
Number of records 159, displaying
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1.
Jenihhin, Maksim
2.
Andrijaškin, Maksim
3.
Antonov, Maksim
4.
Butsenko, Maksim
5.
Gorev, Maksim
6.
Maksim, Antonov
7.
Maksim, I.
8.
Maksim, Tiit
9.
Mõttus, Maksim
10.
Ošeka, Maksim
11.
Radzvilovits, Maksim
12.
Ruchkin, Maksim
13.
Saat, Maksim
14.
Säkki, Maksim
15.
Zelenski, Maksim
CV
9
1.
Jenihhin, Maksim 1981
2.
Antonov, Maksim 1978
3.
Butsenko, Maksim
4.
Gazizov, Maksim 1918
5.
Oseka, Maksim
6.
Osheka, Maksim
7.
Ošeka, Maksim 1988
8.
Saat, Maksim 1944
9.
Säkki, Maksim 1977
name of the person
6
1.
Jenihhin, Maksim
2.
Antonov, Maksim
3.
Butsenko, Maksim
4.
Gorev, Maksim
5.
Gorki, Maksim, pseud., 1868-1936
6.
Saat, Maksim
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