Searching - TalTech Research Portal

Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles

Research Groups

Help and information

Advanced search

high-level fault coverage (keyword)

—

—

Add criteria Simple search filter

Clear

types of item

book ..

journal article ..

newspaper article ..

book article ..

dissertation ..

Open Access ..

Scientific publication ..

year

year of publication

Loading..

Loading..

TTÜ department

Loading..

Loading..

Loading..

name of the person

Loading..

Loading..

Clear

Number of records 4
Look more.. (1/113)
Export

export all inquiry results (4)
Save TXT fail

Save PDF fail

print
Open for editing with marked entries my bookmarks

display

sort
1

journal article

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

journal article
2

book article

High-level test generation for processing elements in many-core systemsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Azad, Siavoosh Payandeh; Raik, Jaan12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2017), July 12-14, 2017, Madrid, Spain : proceedings2017 / 8 p. : ill http://dx.doi.org/10.1109/ReCoSoC.2017.8016156

book article
3

book article

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

book article
4

book article EST / book article ENG

On test generation for microprocessors for extended class of functional faultsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers2020 / p. 21-44 https://doi.org/10.1007/978-3-030-53273-4 Conference proceedings at Scopus Article at Scopus

book article EST / book article ENG

Number of records 4, displaying 1 - 4

1. high-level fault coverage
2. high-level control fault model
3. high-level fault model
4. high-level fault simulation
5. high-level functional fault model
6. fault coverage
7. logic level and high level BDDs
8. low-level fault redundancy
9. high level DD (HLDD)
10. high level synthesis
11. high-level control faults
12. high-level decision diagram
13. high-level decision diagrams
14. high-level decision diagrams (HLDD) synthesis
15. high-level expert group on AI
16. High-Level Synthesis (HLS)
17. high-level synthesis for test
18. high-level test data generation
19. High-Pressure High-Temperature Spark Plasma Sintering
20. code coverage
21. code-coverage
22. conceptual coverage
23. coverage
24. coverage factor
25. diagnostic coverage
26. gaps in coverage
27. insurance coverage
28. NB-IoT coverage
29. Security Coverage
30. stress coverage
31. test coverage
32. 5G coverage
33. asynchronous fault detection
34. automatic fault diagnosis
35. bearing fault diagnosis
36. bi-directional fault monitoring devices
37. conditional fault collapsing
38. control fault models
39. critical path fault tracing
40. cross-layer fault tolerance
41. cross-layered fault management
42. extended fault class
43. fault currents
44. fault analysis
45. fault analysis model
46. fault classification
47. fault classification
48. fault collapsing
49. fault compensation
50. fault current and voltage measurements
51. Fault current limite
52. fault current limiter
53. fault detection
54. fault detection and diagnoses
55. fault detection and diagnosis
56. fault diagnosis
57. fault diagnostic
58. fault diagnostic resolution
59. fault diagnostics
60. fault dignosis
61. fault effects
62. fault emulation
63. fault equivalence and dominance
64. fault handling
65. fault handling strategy
66. fault indicator
67. fault injection
68. Fault Injection Simulation
69. fault Interruption
70. fault localization
71. fault management
72. fault masking
73. fault modeling
74. fault models
75. fault monitoring
76. fault prediction
77. fault protection
78. fault redundancy
79. fault resilience
80. fault ride through
81. Fault ride through enhancement
82. fault signal
83. fault simulastion
84. fault simulation
85. fault simulation with critical path tracing
86. fault tolerance
87. fault tolerant
88. fault tolerant control
89. fault tolerant operation
90. fault tolerant router design
91. fault tolerant systems
92. Fault Tree Analysis
93. fault-injection attack
94. fault-plane solution
95. fault-resilience
96. fault-resistant
97. fault-ride-through (FRT)
98. fault-tolerance
99. fault-tolerant
100. Fault-tolerant (FT) converters
101. fault-tolerant control
102. fault-tolerant converter
103. functional fault model
104. Katun fault
105. no fault found
106. No-Fault-Found
107. open circuit fault
108. parallel fault-simulation
109. short circuit fault
110. stuck-at fault model
111. test generation and fault diagnosis
112. transient fault mitigation
113. transmission lines fault

vaste

sort

Otsing
Valikud 0

year of publication

author

TTÜ department

subject term

series

name of the person

keyword

TalTech Library

Akadeemia tee 1

13519

TalTech homepage TalTech Library homepage Digikogu Digiteek Repository

6203551

data@taltech.ee

TalTech Raamatukogu