Toggle navigation
Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles
Intranet
Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles
Intranet
Databases
Publications
Searching
My bookmarks
0
gate-level analysis (keyword)
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
All fields
Source search
Author search
Subject term search
Title search
starts with
containes
exact match
—
Add criteria
Advanced search
filter
Clear
×
types of item
book
..
journal article
..
newspaper article
..
book article
..
dissertation
..
Open Access
..
Scientific publications
..
year
year of publication
Loading..
author
Loading..
TalTech department
Loading..
subject term
Loading..
series
Loading..
name of the person
Loading..
keyword
Loading..
Clear
Number of records
3
Look more..
(2/164)
Export
export all inquiry results
(3)
Save TXT fail
print
Open for editing with marked entries
my bookmarks
display
Bibliographic view
Short view
sort
author ascending
author descending
year of publication ascending
year of publication descending
title ascending
title descending
1
journal article EST
/
journal article ENG
Fast identification of true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Jürimägi, Lembit
Microelectronics reliability
2018
/
p. 252-261 : ill
https://doi.org/10.1016/j.microrel.2017.11.027
Journal metrics at Scopus
Article at Scopus
Journal metrics at WOS
Article at WOS
journal article EST
/
journal article ENG
2
book article
Hierarchical timing-critical paths analysis in sequential circuits
Jürimägi, Lembit
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
;
Devadze, Sergei
;
Kostin, Sergei
2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain
2018
/
6 p. : ill
https://doi.org/10.1109/PATMOS.2018.8464176
book article
3
book article
A scalable technique to identify true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany
2017
/
p. 152-157 : ill
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553
book article
Number of records 3, displaying
1 - 3
keyword
163
1.
gate-level analysis
2.
gate-level circuit abstraction
3.
gate-level netlist
4.
register transfer and gate level simulation
5.
hierarchical two-level analysis
6.
system-level analysis
7.
logic level and high level BDDs
8.
Field Programmable Gate Array (FPGA)
9.
field programmable gate arrays
10.
field-programmable gate array
11.
Field-Programmable Gate Array (FPGA)
12.
field-programmable gate arrays
13.
field-programmable gate arrays (FPGA)
14.
FPGA (field-programmable gate array)
15.
GaTe
16.
gate and register transfer levels
17.
gate delay
18.
gate driver
19.
Gate Injection Transistor (GIT)
20.
Golden gate assembly
21.
insulated gate bipolar transistors
22.
insulated gate-commutated thyristors
23.
NBTI-critical gate
24.
Opal Kelly field programmable gate array (FPGA)
25.
absolute sea level
26.
airport level of service
27.
arousal level
28.
assurance level
29.
behaviour level test generation
30.
bi-level optimization
31.
CO2 level in classrooms
32.
CO2 level in classrooms and kindergartens
33.
confidence level
34.
country-level logistics
35.
Cross-level Modeling of Faults in Digital Systems
36.
customer compatibility level
37.
deep level
38.
deep level traps
39.
determination of the CO2 level
40.
determining the level of creatine
41.
digitalisation level
42.
distribution-level phasor measurement units (D-PMUs)
43.
education level
44.
exposure level
45.
extreme penetration level of non synchronous generation
46.
extreme sea-level prediction
47.
extreme water level
48.
graduate level
49.
Hierarchical Multi-level Test Generation
50.
high level DD (HLDD)
51.
high level of security
52.
high level synthesis
53.
high-level control fault model
54.
high-level control faults
55.
high-level decision diagram
56.
high-level decision diagrams
57.
high-level decision diagrams (HLDD) synthesis
58.
High-level Decision Diagrams for Modeling Digital Systems
59.
high-level expert group on AI
60.
high-level fault coverage
61.
high-level fault model
62.
high-level fault simulation
63.
high-level functional fault model
64.
high-level synthesis
65.
High-Level Synthesis (HLS)
66.
high-level synthesis for test
67.
high-level test data generation
68.
improvement of safety level at enterprises
69.
improvement of safety level at SMEs
70.
initial level of security
71.
lake level
72.
level control
73.
level crossing
74.
Level of paranoia
75.
level set
76.
level(s) methodology
77.
level-crossing ADC
78.
level-crossing analog-to-digital converters
79.
level-crossing analogue-to-digital converters (ADC)
80.
logic level
81.
lower trophic level models
82.
low-level control system transportation
83.
low-level fault redundancy
84.
low-level radiation
85.
Low-level RF EMF
86.
macro-level industry influences
87.
mean sea level
88.
medium level of security
89.
module level power electronics (MLPE)
90.
module-level power electronics (MLPE)
91.
multi-level governance
92.
multi-level inverter
93.
multi-level leadership
94.
multi-level modeling
95.
multi-level perspective
96.
multi-level perspective of sustainability transitions
97.
multi-level selection and processing environment
98.
noise level
99.
operational level (OL)
100.
Price level
101.
Process/Product Sigma Performance Level (PSPL)
102.
PV module level power electronics
103.
Register Transfer Level - RTL
104.
register transfer level modeling decision diagams
105.
register-transfer level
106.
relative sea level
107.
relative sea level changes
108.
relative sea-level change
109.
RH level
110.
school-level policies
111.
sea level
112.
sea level forecasting
113.
sea level prediction
114.
sea level rise
115.
sea level series
116.
sea level trend
117.
sea level: variations and mean
118.
sea-level
119.
sea-level changes
120.
sea-level equation
121.
Sea-level indicator
122.
sea-level prediction
123.
sea-level rise
124.
sea-level trend
125.
service-level agreements
126.
seven-level multilevel
127.
Sigma performance level
128.
skin conductance level
129.
software level TMR
130.
software security level
131.
steel-level bureaucracy
132.
strategic level decision makers
133.
sufficient level of security
134.
system level
135.
system level hazards
136.
system level test
137.
system planning level
138.
system-level evaluation
139.
task-level uninterrupted presence
140.
three-level
141.
three-level converter
142.
three-level inverter
143.
three-level neutral-point-clamped inverter
144.
three-level NPC inverter
145.
three-level T-type
146.
three-level T-type inverter
147.
three-level T-type quasi-impedance-source inverter (3L-T-type qZSI)
148.
three-level voltage inverter
149.
Tool Confidence Level
150.
top-level domain
151.
transaction-level modeling
152.
treatment level
153.
two-level inverter
154.
undergraduate level
155.
university level informatics education
156.
water level
157.
water level fluctuation
158.
water level measurements
159.
water level reconstruction
160.
water-level changes
161.
voltage level
162.
voltage level optimisation
163.
3-level T-type inverter
subject term
1
1.
Safety Gate
×
match
starts with
ends with
containes
sort
Relevance
ascending
descending
year of publication
author
TalTech department
subject term
series
name of the person
keyword
Otsing
Valikud
0
year of publication
AND
OR
NOT
author
AND
OR
NOT
TalTech department
AND
OR
NOT
subject term
AND
OR
NOT
series
AND
OR
NOT
name of the person
AND
OR
NOT
keyword
AND
OR
NOT